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S1D13717 mobile graphics engine with sd card support hardware functional specification document number: x57a-a-001-03 status: revision 3.02 - epson confidential issue date: 2007/09/18 ? seiko epson corporation 2003-2007. all rights reserved. information in this document is subject to change without notic e. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. seiko epson semiconductor operations div. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/ or international patent laws. epson is a registered trademark of seiko epson corporation. a ll other trademarks are the property of their respective owners free datasheet http:///
page 2 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential free datasheet http:///
epson research and development page 3 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 host cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 direct addressing host interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.2 indirect addressing host interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.3 serial port interface for serial lcd control . . . . . . . . . . . . . . . . . . . . . 14 1.5 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.1 rgb lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 1.5.2 parallel lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.3 serial lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 display features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.7 camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.8 resizers and yuv/rgb converter . . . . . . . . . . . . . . . . . . . . . . 17 1.9 jpeg encoder / decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.9.1 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.9.2 decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.10 2d bitblt engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 host cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 display support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 display features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7 digital video features . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.8 picture input / output functions . . . . . . . . . . . . . . . . . . . . . . . 23 2.9 2d bitblt acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.10 sd memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.11 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.12 power save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.13 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 system diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 free datasheet http:///
page 4 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.1 S1D13717 pinout diagram (fcbga-161) . . . . . . . . . . . . . . . . . . . .30 5.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2.1 unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.2 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.3 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.4 camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.5 sd memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.6 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.7 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2.8 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 summary of configuration options . . . . . . . . . . . . . . . . . . . . . .42 5.4 host interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5 lcd interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . .46 5.6 camera interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . .48 6 d.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 7 a.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.1.1 input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.2 pll clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1.3 internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2 power supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.2.1 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 7.2.2 power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3 host interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.3.1 direct 80 type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.3.2 direct 80 type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3.3 direct 80 type 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.3.4 direct 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3.5 indirect 80 type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3.6 indirect 80 type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.3.7 indirect 80 type 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.8 indirect 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.9 wait length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4 panel interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.4.1 generic tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2 lcd1 nd-tfd, lcd2 8-bit serial interface timing . . . . . . . . . . . . . . . . 92 7.4.3 lcd1 nd-tfd, lcd2 9-bit serial interface timing . . . . . . . . . . . . . . . . 94 7.4.4 lcd1 a-si tft serial interface timing . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.5 lcd1 uwire serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . 97 free datasheet http:///
epson research and development page 5 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.4.6 lcd1, lcd2 parallel interface timing (80) . . . . . . . . . . . . . . . . . . . . . 98 7.4.7 lcd1, lcd2 parallel interface timing (68) . . . . . . . . . . . . . . . . . . . . . 99 7.5 output buffer rise/fall time v.s. capacitance (cl) . . . . . . . . . . . . . . . 100 7.6 camera interface timing . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.6.1 camera interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.2 camera clock output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.6.3 strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.7 sd memory card interface . . . . . . . . . . . . . . . . . . . . . . . . .104 7.7.1 sd memory card access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.7.2 sd memory card clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8 memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.1 main window case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.1.1 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.2 main window case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.2.1 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 8.3 main window, pip+ window, and overlay display . . . . . . . . . . . . . . . 110 8.3.1 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.4 main window, pip+ window, overlay, and yuv . . . . . . . . . . . . . . . . 112 8.4.1 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.5 main window, pip+ window, overlay, and jpeg . . . . . . . . . . . . . . . . 114 8.5.1 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.1 clock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2.1 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.2.2 pixel clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2.4 camera clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.2.5 sd memory card clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.2 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.3 register restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.4.1 system configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.4.2 clock setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 10.4.3 indirect interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 10.4.4 lcd panel interface generic setting registers . . . . . . . . . . . . . . . . . . . . 134 10.4.5 lcd1 setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1 free datasheet http:///
page 6 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.6 lcd2 setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 8 10.4.7 camera interface setting register . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.4.8 display mode setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 10.4.9 gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 10.4.10 overlay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 10.4.11 lut1 (main window) registers . . . . . . . . . . . . . . . . . . . . . . . . . . .192 10.4.12 lut2 (pip+ window) registers . . . . . . . . . . . . . . . . . . . . . . . . . . .193 10.4.13 resizer operation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 10.4.14 jpeg module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9 10.4.15 jpeg fifo setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 10.4.16 jpeg line buffer setting register . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.4.17 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 35 10.4.18 jpeg encode performance register . . . . . . . . . . . . . . . . . . . . . . . . .243 10.4.19 jpeg codec registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 44 10.4.20 sd memory card interface registers . . . . . . . . . . . . . . . . . . . . . . . . .261 10.4.21 2d bitblt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 11 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 11.1 power-on/power-off sequence . . . . . . . . . . . . . . . . . . . . . . . 28 7 11.1.1 power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11.1.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11.1.4 power save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 11.1.5 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 11.1.6 power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 11.2 power save mode function . . . . . . . . . . . . . . . . . . . . . . . . . 290 12 lut architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 12.1 lut1 (main window) for 8 bpp . . . . . . . . . . . . . . . . . . . . . . . 29 1 12.2 lut2 (pip+ window) for 8 bpp architecture . . . . . . . . . . . . . . . . . 292 12.3 lut1 (main window) for 16 bpp architecture . . . . . . . . . . . . . . . . . 293 12.4 lut2 (pip+ window) for 16 bpp architecture . . . . . . . . . . . . . . . . . 294 13 display data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.1 display data for lut mode . . . . . . . . . . . . . . . . . . . . . . . . 295 13.1.1 8 bpp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 13.1.2 16 bpp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 13.2 display data for lut bypass mode . . . . . . . . . . . . . . . . . . . . . 297 13.2.1 8 bpp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 13.2.2 16 bpp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 13.3 display data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.3.1 display buffer data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 free datasheet http:///
epson research and development page 7 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.3.2 bit cover when lut bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.3.3 overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.4 parallel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 13.4.1 8-bit parallel, rgb=3:3:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 13.4.2 8-bit parallel, rgb=4:4:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.4.3 8-bit parallel, rgb=8:8:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.4.4 16-bit parallel, rgb=4:4:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 13.4.5 16-bit parallel, rgb=5:6:5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.4.6 18-bit parallel, rgb=6:6:6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 13.4.7 16-bit parallel, rgb=8:8:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 13.5 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 13.5.1 8-bit serial, rgb=3:3:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 13.5.2 8-bit serial, rgb=4:4:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 13.6 yuv input / output data format . . . . . . . . . . . . . . . . . . . . . . . 30 6 13.6.1 yuv 4:2:2 data input / output format . . . . . . . . . . . . . . . . . . . . . . . . 306 13.6.2 yuv 4:2:0 data input / output format . . . . . . . . . . . . . . . . . . . . . . . . 307 13.7 yuv/rgb conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .309 14 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.1 swivelview modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14.1.1 90 swivelview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 14.1.2 180 swivelview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.1.3 270 swivelview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 15 picture-in-picture plus (pip+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 15.1 overlay display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 15.1.1 overlay display effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 16 2d bitblt engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 20 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 16.2 bitblts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 16.2.1 read bitblt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.2.2 move bitblt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.2.3 pattern fill bitblt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.2.4 solid fill bitblt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 16.2.5 bitblt terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324 16.2.6 source and destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 16.3 data functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 16.3.1 rop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 16.3.2 transparency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 16.4 linear / rectangular . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17 resizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 free datasheet http:///
page 8 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 17.1 trimming function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 17.2 scaling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 17.2.1 1/2 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 17.2.2 1/3 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 17.2.3 1/4 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 17.2.4 1/5 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 17.2.5 1/6 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 17.2.6 1/7 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 17.2.7 1/8 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 17.3 resizer restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 18 digital video functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 18.1 display image data from the camera interface . . . . . . . . . . . . . . . . . 341 18.2 jpeg encode and camera data to the host . . . . . . . . . . . . . . . . . . 342 18.3 jpeg decode and display data from the host . . . . . . . . . . . . . . . . . 343 18.4 jpeg 180 rotate encode diagram . . . . . . . . . . . . . . . . . . . . . 344 19 jpeg encode/decode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.1 jpeg features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.1.1 jpeg fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 19.1.2 jpeg codec interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 7 19.1.3 jpeg bypass modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 8 19.2 example sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.2.1 jpeg encoding process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 19.2.2 jpeg decoding process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 19.2.3 yuv data capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 63 19.2.4 yuv data display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.2.5 exit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 20 camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 20.1 type 1 camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 20.2 strobe control signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 20.2.1 generating a strobe pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7 20.2.2 strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 21 sd memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.1 interface commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 21.2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 22 indirect interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 22.1 using the indirect interface . . . . . . . . . . . . . . . . . . . . . . . . . 372 22.2 example sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 22.2.1 register read/write example sequence . . . . . . . . . . . . . . . . . . . . . . .373 22.2.2 memory write example sequence . . . . . . . . . . . . . . . . . . . . . . . . . .374 free datasheet http:///
epson research and development page 9 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 22.2.3 memory read example sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 376 23 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 24 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 25 sales and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 25.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 free datasheet http:///
page 10 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential free datasheet http:///
epson research and development page 11 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1 introduction 1.1 scope this is the hardware functional specification for the S1D13717 mobile graphics engine. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences: video subsystem designers and software developers. this document is updated as appropriate. please check for the latest revision of this document before beginning any development. the latest revision can be downloaded at www.erd.epson.com. we appreciate your comments on our documentation. please contact us via email at documentation@erd.epson.com. 1.2 general description the S1D13717 is an mobile graphics engine solution designed with support for the digital video revolution in mobile products. the S1D13717 contains an integrated camera interface, hardware jpeg encoder/decoder and sd memory card interface. seamlessly connecting to both direct and indirect cpu interfaces, it provides support for up to two lcd panels. the mobile graphics engine supports all standard tft panel types, elimi- nating the need for an external timing control ic. the S1D13717, with it?s 224k bytes of embedded sram and rich feature set, provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring digital video, such as mobile communications devices and palm-size pdas. additionally, products requiring a rotated display can take advantage of the swivelview tm feature which provides hardware rotation of the display memory, transparent to the software application. the S1D13717 also provides support for ?picture-in-picture plus? (a variable size window with overlay functions). higher performance is provided by the hardware acceleration engine which provides 2d bitblt functions. the S1D13717 provides impressive support for cellular and other mobile solutions requiring digital video support. however, its impartiality to cpu type or operating system makes it an ideal display solution for a wide variety of applications. free datasheet http:///
page 12 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 1.3 internal memory the S1D13717 contains 224k bytes of internal sram memory. this internal memory is divided into two physical sram banks that contain independent arbitration logic. the boundaries between the memory banks are transparent to the user. memory bank1 is 128k bytes and bank2 is 96k bytes. the internal memory can be used in 5 distinct ways: 1. main window display only : 224k bytes available. if the jpeg functions and the pip + window are not required (therefore disabled), the entire 224k bytes of memory is available for main window image storage. in this case, the image written to the main display window can either come from the host (rgb data) over the host interface, and/or input by the camera (yuv or rgb data) through the camera interface. the main window display start address registers (reg[0212h]-[0214h]) determines where the main window image is stored in memory. additionally, if the main window image is being updated by a camera, the yuv/rgb converter write start address registers (reg[0242h]-[0244h]) determines where the camera data is written and typ- ically equals the address of the main window display start address. 2. main window and pip + window display only : 224k bytes available. if the jpeg functions are not required (therefore disabled), the entire 224k bytes of memory is available for image storage and must be shared between the main window display image and the pip + window display image. it is recommended that the main win- dow and the pip + window be located in different memory banks for improved perfor- mance. since the pip + window is typically smaller than the main window, it is recommended that the pip + window display image be set to bank2 using the pip + display start address registers (reg[0218h]-[021ah]), and the main window dis- play image be set to bank1 using the main window display start address registers (reg[0212h]-[0214h]). as in option 1, the image data for either of these windows can come from the host or from the camera. typically, in this setup the camera will input image data to the pip+ window and the yuv/rgb converter write start address registers (reg[0242h]-[0244h]) will equal the pip + display start address. 3. jpeg functions enabled : 192k bytes - jpeg fifo size available. if either the jpeg encoder or decoder is used, segments of bank1 and bank2 are automatically reserved for jpeg use only. the jpeg fifo uses bank1 and its size is configurable from 4k bytes to 128k bytes using the jpeg fifo size bits (reg[09a4h] bits 4-0). the jpeg fifo starts at address 0 of bank1 and is accessed using the jpeg fifo read/write register (reg[09a6h]). the jpeg fifo is used as an interface between the jpeg module and the host. when the S1D13717 is encoding a jpeg image, the jpeg fifo stores jpeg data for the host to read. when the S1D13717 is decoding a jpeg file, the jpeg fifo stores incoming jpeg data from the host. the size of the jpeg fifo should be set to optimize performance based on the host operating speed, S1D13717 operating speed, and the size of the jpeg image. the jpeg line buffer uses the upper 32k bytes of bank2, from 2ffffh - 37fffh. during an encode operation, the jpeg line buffer is used to organize incoming yuv data from the camera and send it to the jpeg encoder. during a decode operation, the jpeg line buffer organizes the yuv data output of the jpeg decoder to be sent to the view re- sizer and yuv/rgb converter for display on the lcd panel. free datasheet http:///
epson research and development page 13 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 4. yuv data output : 192k bytes - jpeg fifo size available. if yuv data from the camera is directly sent to the host, the jpeg codec is bypassed, however the jpeg fifo and jpeg line buffer are still utilized. the jpeg fifo and jpeg line buffer are used as described for the decode operation in option 3 (jpeg functions enabled). 5. yuv data input : 192k bytes available. if yuv data from the host is sent directly to the S1D13717, the jpeg codec and jpeg fifo are bypassed. yuv data is written directly to the jpeg line buffer. in this mode, the jpeg line buffer is accessed us- ing the jpeg line buffer write port register (reg[09e0h]). the jpeg line buffer then sends the yuv data to the view resizer and the yuv/rgb converter for dis- play on the lcd panel. all data stored in the internal memory that is intended for display on the lcd panel, must be stored in rgb format. yuv data from the camera interface or from the host must be converted to rgb by the yuv/rgb converter. color depth data formats of 8/16/32 bit- per-pixel are supported. 1.4 host cpu interface the S1D13717 supports four cpu host interfaces with 16-bit wide data buses. each interface can support little or big endian data formats, direct or indirect addressing, and the option to use a wait signal or not. see section 5.3, ?summary of configuration options? on page 42 for a description on how to configure the S1D13717 for these various options. in addition to these four cpu host interfaces, the S1D13717 also has a serial cpu port which allows the cpu host to directly control a serial lcd panel connected to the S1D13717. the host cpu that is connected to the S1D13717 must meet all specified timing parameters for the host interface being used, as shown in section 7.3, ?host interface timing? on page 56. it is recommended that the wait# signal be used for all host interfaces as this will ensure that the highest performance is achieved when accessing the S1D13717. when this mode is selected, the wait# signal is only asserted when needed (i.e. the S1D13717 cannot accept or present data immediately). if the wait# signal is not used, the cpu must guarantee that all cycles meet the maximum cycle length as shown in table 7-46: ?wait length,? on page 88. free datasheet http:///
page 14 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 1.4.1 direct addressing host interfaces the direct addressing host interfaces (direct 80 type 1, direct 80 type 2, direct 80 type 3, and direct 68) are generic asynchronous cpu interfaces that provide addressing along with the data in one transfer. these interfaces only differ in the signals used to interpret the read/write and byte enable command signals. typically, these interfaces are used to connect to the external memory bus of the host cpu and offer the highest performance when accessing the S1D13717. the direct addressing host interfaces also have the ability to combine the S1D13717 registers and internal memory into one contiguous memory segment or into separate memory segments. in the contiguous mode (1 cs# mode), only one chip select is used to select the S1D13717 on the host bus. memory and register accesses are differentiated by the m/r# pin which is typically connected to address pin a19 of the host cpu bus. in the separate memory mode (2 cs# mode), two chip selects select the S1D13717. one chip select is used for memory accesses and the other is used for register accesses. in this mode, the host cpu can be programmed to assign different memory spaces for the memory and registers of the S1D13717. 1.4.2 indirect addressing host interfaces the indirect addressing host interfaces (indirect 80 type 1, indirect 80 type 2, indirect 80 type 3, and indirect 68) are generic asynchronous cpu interfaces that provide addressing and data in two separate transfers. these interfaces only differ in the signals used to interpret the read/write and byte enable command signals. typically, these interfaces are used when the address and data lines of the host cpu are multiplexed together and two transfers are needed to complete a data transfer. 1.4.3 serial port interface for serial lcd control the S1D13717 also supports a serial host interface that is used to directly control a serial lcd panel connected to the S1D13717. this bypass mode is controlled by the serial port bypass enable bit (reg[0032h] bit 8). typically, this interface is used when the S1D13717 is in power save mode and a serial lcd panel is required to show an image such as a status display. free datasheet http:///
epson research and development page 15 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1.5 lcd controller the S1D13717 mobile graphics engine contains a versatile lcd controller which supports many lcd panel types and offers a rich feature set. the S1D13717 has four lcd interface modes where either one or two lcd panels (referred to as lcd1 and lcd2) can be connected to the S1D13717. these modes are selected using the panel interface bits (reg[0032h] bits 1-0). lcd1 and lcd2 each have their own vertical and horizontal lcd panel size setting and other specific features, in order to easily switch from the lcd1 panel display to the lcd2 panel display or vice versa. in mode 1, lcd1 is defined as a tft rgb type lcd panel. lcd2 is defined as a serial interface type lcd panel with integrated ram to store the image data. in mode 2, lcd1 is defined as a parallel interface lcd panel with integrated ram to store the image data. lcd2 is defined as a serial interface type lcd panel with integrated ram to store the image data. in mode 3, lcd1 and lcd2 are both defined as parallel interface lcd panels with integrated ram to store the image data. in mode 4, lcd1 is defined as a tft rgb type lcd panel. lcd2 is defined as a parallel interface lcd panel with integrated ram to store the image data. in each mode, only one display at a time (lcd1 or lcd2) can be the active display. a typical application for using two separate lcd panels would be a clamshell type cellular phone where there is a main display and a smaller status display on the outside of the phone. lcd1 would be the main display and lcd2 would be the small status display, typically a serial interface lcd panel. two images would be stored in the internal memory of the S1D13717 for each lcd display. when each display is selected as active, (lcd1 when the cellular phone is open and lcd2 when the cellular phone is closed) the correct image to be displayed is selected using the main window display start address registers (reg[0210h]-[0212h]). for lcd interface pin mapping refer to table 5-13: ?lcd interface pin mapping,? on page 46. 1.5.1 rgb lcd interface the rgb lcd interface supports a wide range of generic tft panels. tft panels that can be programmed via various serial type interface are supported and are selected with the lcd1 serial data type bits (reg[0054h] bits 7-5). the rgb lcd panel data bus width is selectable to support 9/12/16/18-bit panels using the rgb interface panel data bus width bits (reg[0032h] bits 6-4). other configurable options include non-display period times and polarity, width, and position of control signals. free datasheet http:///
page 16 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 1.5.2 parallel lcd interface the parallel lcd interface supports multiple output data formats, providing the flexibility to support various ram integrated parallel interface lcd panels. if a parallel panel is connected to lcd1, the lcd1 parallel data format bits (reg[0056h] bits 2-0) are used to program the output data format, otherwise the lcd2 parallel data format bits (reg[005eh] bits 2-0) are used. the lcd panel image can be updated in three different ways. manual transfer is accom- plished by setting reg[003ah] bit 1 = 1 which sends one frame of panel data to the parallel lcd panel. lcd module vsync manual transfer mode synchronizes a manual frame transfer to an external vsync signal sent by the parallel lcd panel. the vsync input enable bit for either lcd1 or lcd2 (reg[0056h] bit 7 or reg[005eh] bit 7) must be set to enable this mode. the last transfer method is automatic transfer which sends frames to the lcd panel whenever a camera vertical sync signal is detected. if the vysnc input mode is also enabled, an external lcd panel vsync must also be detected. automatic transfer mode is enabled by setting reg[003ch] bit 1 = 1. automatic transfer mode is intended for displaying a camera image on a serial or parallel interface lcd panel without the need to manually update the panel display. 1.5.3 serial lcd interface the serial lcd interface supports serial type lcd panels only on lcd2. serial data type, data direction, data format, and serial clock phase and polarity are all selectable and are controlled in the lcd2 serial interface setting register (reg[005ch]). serial interface panels are updated with image data as described in section 1.5.2, ?parallel lcd interface? on page 16. 1.6 display features the S1D13717 contains display features that enhance the functionality of the mobile graphics engine. these features are picture-in-picture plus (pip + ), overlay, swivelview, mirror, and pixel doubling. pip + is a sub-window within the main window and typically is used to display the camera image or a decoded jpeg image. pip + can be used with the overlay functions so that only the part of the pip + window that overlaps the overlay color in the main window is displayed (according to the overlay function selected). various overlay functions can be employed such as transparency, averaging, anding, oring, and inverting. multiple overlay functions can be enabled, but only the overlay function with the highest priority is processed. swivelview is a hardware rotation of the display image by either 90, 180, or 270 degrees. by processing the rotation of the image in hardware, swivelview offers a performance advantage over software rotation. swivelview can be used to support portrait sized panels mounted in a landscape orientation or vice versa. free datasheet http:///
epson research and development page 17 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential mirror can be used to mirror the image in either the pip + window display, main window display, or both. a typical application for mirroring is to support swivelling on a clamshell phone. when the large display is on the outside of the phone and the camera is pointing at the user, mirroring allows the camera image to be displayed properly. pixel doubling is a feature that can be used to double the size of an image in either the pip + window display, main window display or both. typical applications for pixel doubling include increasing the displayed size of a decoded jpeg image or using a larger panel size than is supported natively by an operating system. for example, if a 320x320 resolution panel is used with an os that supports only a main display of 160x160 (such as in many pdas), pixel doubling can be enabled to utilize the whole display. 1.7 camera interface the S1D13717 supports an 8-bit parallel camera interface. the input data format supported is yuv 4:2:2. embedded sync signals, as defined by the itu-r bt656 standard, are also supported. a clock is supplied to the camera from the camera interface (cmclkout) and the camera in turn outputs yuv data, horizontal and vertical sync signals, and a pixel clock that the S1D13717 camera interface uses to sample the incoming yuv data. the cmclkout frequencies are controlled by the camera clock divide select bits (reg[0100h] bits 3-0). the camera interface supports various types of yuv cameras by allowing the selection of different formats of yuv 4:2:2 signals. features such as yuv data format, yuv data range, hsync and vsync polarity, and camera pixel clock input polarity are all selectable. since the camera pixel clock can be, at most, 1/3 the s1d13715 system clock , the frames per second of the camera image displayed on the lcd display is dependant on the internal speed of the S1D13717. for example, a setting of 54mhz for the system clock results in the camera returning a pixel clock of 6.5mhz when the S1D13717 camera clock out divide is set to a divide of 4 (typical cameras use a divide by 2 of the input clock to generate the pixel clock). for cif resolutions (352x288), this translates into 29 fps. for a camera clock out divide of 2 and vga resolutions (640x480), 21 fps is achieved. 1.8 resizers and yuv/rgb converter there are two resizers in the S1D13717: the view resizer and the capture resizer. both resizers can be used to resize (crop) and/or scale incoming yuv data from the camera interface, from the jpeg decoder, or from the host cpu in yuv bypass mode. once the yuv data has been resized and scaled, it gets converted to rgb data by the yuv/rgb converter (yrc), so that it can be displayed on the lcd panel. the location in memory where the yrc writes the rgb data is defined by the yuv/rgb converter write start address registers (reg[0242h]-[0244h]). the output bpp of the yrc must match either the main window color depth (bpp) or the pip + window color depth (bpp) setting, depending on which window the image is being displayed in. the yrc color depth (bpp) output is controlled by the yrc output bpp select bits (reg[0240h] bits 11-10). the resizers can support a maximum image size up to 2048 x 2048 pixels. free datasheet http:///
page 18 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential although each resizer can be configured to be the source for the yrc using the output source select bit (reg[0940h] bit 3), typically the view resizer is set as the source since only the capture resizer can be the source for the jpeg encoder or for yuv bypass mode to the host cpu. a typical application has the view resizer resizing the camera data and has the yrc converting it for display on the lcd panel, while the capture resizer is used to send camera yuv data for jpeg encoding or for raw storage by the host cpu. when the desired viewed camera image is the same dimensions as the desired captured jpeg or yuv image, only the capture resizer needs to be used. note only the view resizer can be used to resize yuv data from the jpeg decoder or from the host cpu. 1.9 jpeg encoder / decoder the S1D13717 contains a full jpeg codec capable of encoding an incoming camera data stream or decoding a jpeg image sent from the host cpu. 1.9.1 encoder either the yuv data stream from the camera interface or the display buffer memory via the rgb to yuv converter or yuv data from the host can be encoded into a jpeg image. the yuv data from the capture resizer is organized into 8 x 8 blocks in the jpeg line buffer, as required for jpeg processing, and then sent to the jpeg encoder. as the jpeg encoder is encoding the yuv data, it starts filling up the jpeg fifo with jpeg data. this data must be read by the host cpu before the jpeg fifo overflows. status flags and interrupts can be used to determine how full the jpeg fifo is becoming. the jpeg fifo is accessed through the jpeg fifo read/write register (reg[09a6h]). the jpeg fifo can be set as large as 128k bytes and typically this will be large enough to contain the whole jpeg image. a smaller jpeg file size can be achieved using the capture resizer?s trimming and scaling functions or a higher jpeg compression ratio can be achieved by using different quantization and huffman tables. as mentioned in section 1.3, ?internal memory? on page 12, when the jpeg functions are enabled, 32k bytes of the internal memory is used for the jpeg line buffer and from 4k bytes to 64k bytes is used for the jpeg fifo. the jpeg encoder can encode yuv 4:2:2, yuv 4:2:0, and yuv 4:1:1 data formats and will convert the incoming yuv data to the desired format. this encoding option is set by the yuv format select bits (reg[1000h] bits 1-0). the jpeg file size can be reduced if a smaller uv:y ratio format is used. the intended use of the jpeg encoder is to ?take a snapshot? of the currently viewed camera image or display image, or to encode yuv data sent by the host cpu. this jpeg image is then downloaded to the host cpu through the jpeg fifo and stored as a jpeg file. free datasheet http:///
epson research and development page 19 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1.9.2 decoder the S1D13717 contains a jpeg decoder which allows the host cpu to send a jpeg image file for conversion and display on the lcd panel, or to send the resulting yuv decoded data back to the host cpu. the incoming jpeg data is written to the jpep fifo and then goes to the jpeg decoder for decoding into yuv format. the yuv format output is based on the original format the jpeg file was encoded from and is reported in the yuv format select bits (reg[1000h] bits 1-0). the output of the jpeg decoder goes to the jpeg line buffer which then organizes the 8 x 8 blocks of yuv data into the correct yuv format and sends this data to the view resizer. the view resizer can trim and scale the image and then it is converted by the yrc to be displayed on the lcd panel or sent to the host cpu. while writing the jpeg data to the jpeg fifo, the host cpu may be interrupted. when this happens, the jpeg decoder completes decoding the data stored in the jpeg fifo and the waits for more data from the host cpu. the decode operation will continue until the jpeg decoder detects the end-of-file marker. the jpeg fifo must not be overflowed by the host cpu. status flags and interrupts can be used to determine how full the jpeg fifo is becoming. the jpeg fifo is accessed through the jpeg fifo read/write register (reg[09a6h]). as mentioned in section 1.3, ?internal memory? on page 12, when the jpeg functions are enabled, 32k bytes of the internal memory is used for the jpeg line buffer and from 4k bytes to 64k bytes is used for the jpeg fifo. the jpeg decoder can decode yuv 4:4:4, yuv 4:2:2, yuv 4:2:0, and yuv 4:1:1 data formats. 1.10 2d bitblt engine the purpose of the 2d bitblt engine is to improve the overall system performance by off- loading the work of the host cpu in moving display data between the cpu and display memory. there are five bitblts (bit block load transfer) that can move display data from one location to another. additionally, data functions can be performed that manipulate the source and/or destination data. for more information on the 2d bitblt engine, see section 16, ?2d bitblt engine? on page 320. free datasheet http:///
page 20 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 2 features 2.1 internal memory ? embedded 224k byte sram memory used for: ?display buffer ? jpeg fifo ?jpeg line buffer 2.2 host cpu interface ? four generic asynchronous cpu interfaces ? 16-bit data bus ? 16-bit register and fifo access ? 8/16-bit display buffer access ? direct / indirect addressing ? little / big endian support ? registers are memory-mapped ? m/r# input selects between memory and register address space ? m/r# and cs# inputs select between memory and register address space in 2 cs# mode ? cpu serial port for direct control of a serial lcd ? cpu parallel port for direct control of a parallel lcd 2.3 display support ? active matrix tft displays: 9/12/18-bit interface ? tft with u-wire interface ? a-si tft interface ? epson nd-tfd interface ? 8/9-bit serial interface lcds with integrated ram ? 8/16/18-bit mpu parallel interface lcds with integrated ram ? supports a maximum of 2 panels (lcd1 and lcd2 can?t be refreshed simultaneously) free datasheet http:///
epson research and development page 21 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 2.4 display modes ? supports three panel interface modes which each allow two lcds (lcd1 and lcd2) to be connected to the S1D13717. only one lcd can be active at a time. ? mode 1: ? lcd1: rgb type panel ? lcd2: serial interface panel ? mode 2: ? lcd1: parallel interface panel ? lcd2: serial interface panel ? mode 3: ? lcd1: parallel interface panel ? lcd2: parallel interface panel ? mode 4: ? lcd1: rgb type panel ? lcd2: parallel interface panel ? host cpu can directly control serial interface panels on lcd2 ? host cpu can directly control parallel interface panels on lcd1 or lcd2 ? 8/16/32 bit-per-pixel (bpp) color depths ? separate look-up tables (luts) for the main window and the pip + window ? luts can be bypassed 2.5 display features ? overlay functions ? swivelview?: 90, 180, 270 counter-clockwise hardware rotation of display image ? mirror display: provides a ?mirror? image of the display ? virtual display support: displays images larger than the panel size through the use of panning and scrolling ? picture-in-picture plus (pip + ): displays a variable size window overlaid over back- ground image ? pixel doubling ? video invert: data output to the lcd is inverted free datasheet http:///
page 22 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 2.6 camera interface ? 8-bit camera interface (yuv multi out) ? supports yuv 4:2:2 format ? supports itu-r bt.656 format ? mpu type interface camera support on camera interface ? strobe control function 2.7 digital video features ? hardware jpeg codec based on the jpeg baseline standard ? jpeg encode supports yuv 4:2:2, yuv 4:2:0, yuv4:1:1 formats ? jpeg decode supports yuv 4:4:4, yuv 4:2:2, yuv 4:2:0, yuv4:1:1 formats ? arithmetic accuracy satisfies the compatibility test of jpeg part-2 ? software control of image size ? maximum horizontal image size for jpeg encoding (yuv 4:2:2 format: up to 2880 pixels) ? two resizers: view resizer receives yuv data from the camera interface, or from the jpeg decoder, or from the host cpu. capture resizer receives yuv data only from the camera interface. ? yuv data can be resized (trimmed and scaled) then: ? converted to rgb data for display on the lcd ? converted to jpeg data and read by the cpu host via the jpeg fifo ? read by the host cpu directly (yuv format) ? yuv to rgb converter (yrc): yuv data from the view resizer or capture resizer is converted to rgb format to be displayed on the lcd. free datasheet http:///
epson research and development page 23 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 2.8 picture input / output functions ? the yuv data from camera interface can be: ? stored in the display buffer after resizing and conversion to rgb format. ? transferred to the host cpu via the jpeg fifo after resizing and encoding to jpeg format. ? transferred to the host cpu via the jpeg fifo after resizing and conversion to yuv format (4:2:2, 4:2:0) . ? the jpeg file downloaded from the host cpu can be: ? decoded by the internal jpeg decoder, resized, scaled, converted to rgb and stored in the display buffer memory for display on the lcd. ? decoded by the internal jpeg decoder, resized, scaled, and downloaded to the host cpu via the jpeg fifo. ? yuv data (format 4:2:2 or 4:2:0) downloaded from the host cpu can be: ? resized, scaled, converted to rgb and stored in the display buffer memory for dis- play on the lcd. ? encoded by the internal jpeg encoder, resized, scaled, and downloaded to the host cpu via the jpeg fifo. ? rgb data in the display buffer can be: ? converted to yuv, then transferred to the host cpu via the jpeg fifo after resizing and encoding to jpeg format. 2.9 2d bitblt acceleration ? 2d bitblt engine including: (this function does not support 32 bpp modes) move bitblt transparent move bitblt solid fill bitblt read bitblt pattern fill bitblt move bitblt with color expansion 2.10 sd memory card interface ? sd memory card interface compatible with the sd memory card physical layer version 1.0 specification ? 4-bit or 1-bit interface (spi mode is not supported) ? no security functions ? card detect and write protect inputs free datasheet http:///
page 24 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 2.11 clock ? internal pll driven by a single external reference clock, 32.768khz ? 40 - 55mhz pll output ? pll bypass mode for external clock input 2.12 power save ? software initiated power save mode ? software initiated display blank 2.13 miscellaneous ? general purpose input/output pins are available ? fcbga 161-pin package free datasheet http:///
epson research and development page 25 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 3 system diagrams figure 3-1: S1D13717 system diagram 1 a[17:1] csn a[18] rdb wrb ewait intpn ab[17:1] db[15:0] cs# m/r# rd# we# be1# be0# int reset# scs# sclk sa0 si wait# cpu (type1) S1D13717 clki 32.768khz d[15:0] scklcd solcd rsto csn a0lcd ubenb lbenb cmclkout cmvref cmhref cmclkin cmdat[7:0] camera vref href mclk pclk yuv[7:0] strobe cmstrout sdclk sdgpo sdcd# sdwp sdcmd sd memory card fpsck fpa0 fpso mclk lcd2(serial) xcs sck a0 si fpcs2x fpvsync fphsync fpdat[17:0] fpdclk fpdrdy lcd1(generic tft) vsync hsync dclk enab r5~r0 g5~g0 b5~b0 led/powerc mwp cmd dat[3:0] xmcd sddat[3:0] free datasheet http:///
page 26 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 3-2: S1D13717 system diagram 2 ab[17:1] db[15:0] cs# m/r# hiovdd we# be1# be0# int reset# scs# sclk sa0 si wait# cpu (type2) S1D13717 clki 32.768khz cmclkout cmvref cmhref cmclkin cmdat[7:0] camera1 vref href mclk pclk yuv[7:0] strobe cmstrout fpvsync fphsync fpdat[17:0] fpdclk fpdrdy lcd1(nd-tfd) fpcs1x fpsck fpa0 fpso vsync hsync dck enab r5~r0 g5~g0 b5~b0 xcs sck a0 si lcd2(serial) xcs sck a0 si fpcs2x a[17:1] csn a[18] rdz ewait intpn d[15:0] scklcd solcd rsto csn a0lcd wrz1 wrz0 rd# sdclk sdgpo sdcd# sdwp sdcmd sd memory card mclk led/powerc mwp cmd dat[3:0] xmcd sddat[3:0] free datasheet http:///
epson research and development page 27 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 3-3: S1D13717 system diagram 3 ab[17:1] db[15:0] cs# m/r# rd# we# be1# be0# int reset# scs# sclk sa0 si wait# cpu (type1) S1D13717 clki 32.768khz cmclkout cmvref cmhref cmclkin cmdat[7:0] camera1 vref href mclk pclk yuv[7:0] strobe cmstrout fpcs1x fpvsync fpdat[15:0] lcd1(parallel) fpvin1 fphsync xcs xwr d[15:0] a0 vsync lcd2(serial) xcs sck a0 si fpsck fpa0 fpso fpcs2x a[17:1] csn a[18] rdb wrb ewait intpn d[15:0] scklcd solcd rsto csn a0lcd ubenb lbenb xrd vdd sdclk sdgpo sdcd# sdwp sdcmd sd memory card mclk led/powerc mwp cmd dat[3:0] xmcd sddat[3:0] free datasheet http:///
page 28 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 3-4: S1D13717 system diagram 4 ab[17:1] db[15:0] cs# m/r# rd# we# be1# be0# int reset# wait# cpu (type1) S1D13717 clki 32.768khz cmclkout cmvref cmhref cmclkin cmdat[7:0] camera1 vref href mclk pclk yuv[7:0] strobe cmstrout fpcs1x fpvsync fpdat[15:0] lcd1(parallel) fpvin1 fphsync fpcs2x fpvin2 lcd2(parallel) a[17:1] csn a[18] rdb wrb ewait intpn d[15:0] rsto ubenb lbenb xcs xwr d[15:0] a0 vsync xrd vdd xcs xwr d[15:0] a0 vsync xrd vdd sdclk sdgpo sdcd# sdwp sdcmd sd memory card mclk led/powerc mwp cmd dat[3:0] xmcd sddat[3:0] free datasheet http:///
epson research and development page 29 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 4 block diagram figure 4-1: S1D13717 block diagram camera i/f jpeg codec capture yuv/rgb rgb i/f serial i/f 2d display fifo lut1 host i/f display buffer lut2 p/s gpio main lcd or sub lcd main & sub lcd (serial) (parallel) serial input cpu bus camera sd memory (rgb) system clock (pll) camera clock line buffer fifo bitblt parallel i/f lcd bias, led etc. embedded sram sd memory card i/f card resizer pixel clock serial clock sd card clock view resizer free datasheet http:///
page 30 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5 pins 5.1 S1D13717 pinout diagram (fcbga-161) figure 5-1: S1D13717 fcbga-161 pin mapping table 5-1: S1D13717 fcbga-161 pin mapping p nc nc cmstrout sdcmd sddat1 sddat3 sdgpo corevdd cmdat3 cmdat4 ciovdd vss nc nc n nc nc vss vss sddat0 vss cmclkout cmhref cmdat1 cmdat5 cnf3 cnf4 nc nc m testen corevdd sdwp sdclk siovdd siovdd cmclkin cmvref cmdat2 cmdat6 cnf5 cnf6 pllvss vcp l cnf0 cnf2 scanen gpio3 sdcd# sddat2 vss cmdat0 vss cmdat7 sclk clki pllvdd corevdd k vss gpio2 cnf1 gpio0 int si scs# sa0 j fpdat17 piovdd gpio1 fpdat16 be0# reset# wait# vss h vss fpdat14 fpdat15 fpdat13 rd# be1# we# m/r# g fpdat12 fpdat10 fpdat9 fpdat11 cs# db1 db0 hiovdd f fpdat8 fpdat7 fpdat5 corevdd db2 db5 db3 vss e fpdat3 fpdat4 fpdat1 fpdat6 nc db4 db9 corevdd db7 d fpdat2 fpdat0 fpframe vss fpa0 fpvin2 hiovdd ab9 ab6 vss db6 db10 vss db8 c fpline piovdd drdy fpcs2# fpso ab16 ab13 vss ab7 ab3 db15 hiovdd db12 db11 b nc nc fpcs1# vss fpvin1 ab15 ab12 ab11 ab8 ab4 ab1 db14 nc nc a nc nc fpshift fpsclk corevdd ab17 ab14 ab10 corevdd ab5 ab2 db13 nc nc 1234567891011121314 l k j h g f e d c b a m n 1234567891011121314 p bottom view this mark is for reference only and does not appear on the bottom of the package. free datasheet http:///
epson research and development page 31 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 5.2 pin descriptions key: 1. lvcmos is low voltage cmos (see section 6, ?d.c. characteristics? on page 49). 5.2.1 unused pins all unused input pins should be connected to their inactive state if an internal pull-down resistor is not present. all unused output pins should be left unconnected. all unused bi-directional pins should be connected to a 100k pull-down/up resistor if an internal pull-down resistor is not present. i = input o=output io = bi-directional (input/output) p=power pin z = high impedance l = low level output h = high level output 0 = pull-down control on input 1 = pull-up control on input table 5-2: cell descriptions item description ic lvcmos 1 input icu lvcmos input with pull-up resistor (60k @3.0v) icd lvcmos input with pull-down resistor (60k @3.0v) ihcs h system lvcmos level schmitt input ilcs l system lvcmos level schmitt input oln35 low noise output buffer (3.5ma/-3.5ma@3.0v) oln35t low noise tri-state output buffer (3.5ma/-3.5ma@3.0v) blnc35 low noise lvcmos io buffer (3.5ma/-3.5ma@3.0v) blnc35d low noise lvcmos io buffer (3.5ma/-3.5ma@3.0v) with pull-down resistor (60k @3.0v) blnc35ds low noise lvcmos schmitt io buffer (3.5ma/-3.5ma@3.0v) with pull-down resistor (60k @3.0v) itd test mode control input with pull-down resistor (60k @3.0v) iltr low voltage transparent input ihtr high voltage transparent input ohtr high voltage transparent output free datasheet http:///
page 32 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.2.2 host interface many of the host interface pins have different functions depending on the selection of the host bus interface (see configuration of cnf[4:2] pins in table 5-10: ?summary of power- on/reset options,? on page 42). for a summary of host interface pins, see table 5-11: ?host interface pin mapping (1 cs# mode),? on page 44 and table 5-12: ?host interface pin mapping (2 cs# mode),? on page 45. table 5-3: host interface pin descriptions pin name type fcbga pin# cell power reset# state description ab[17:2] i a6,c6,b6, a7,c7,b7, b8,a8,d8, b9,c9,d9, a10,b10, c10,a11, b11 ic hiovdd z system address bits 17:2. ? for indirect host bus interfaces, these pins must be connected to v ss . ab1 i b11 ic hiovdd z system address bit 1. ? for indirect host bus interfaces, this pin is the command/data signal. db[15:0] io c11,b12, a12,c13, c14,d12, e12,d14, e14,d11, f12,e11, f13,f11, g12,g13 blnc35 hiovdd z system data bus. cs# i g11 ic hiovdd z this input pin has multiple functions. ? for 1 cs# mode, this pin inputs the chip select signal (cs#). ? for 2 cs# mode, this pin inputs the memory chip select signal (csm#). m/r# i h14 ic hiovdd z this input pin has multiple functions. ? for 1 cs# mode, this pin selects between the display buffer and register address spaces. when m/r# is set high, the display buffer is accessed and when m/r# is set low the regis- ters are accessed. ? for 2 cs# mode, this pin inputs the register chip select (csr#). ? for indirect host bus interfaces, this pin must be connected to v ss . free datasheet http:///
epson research and development page 33 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential rd# i h11 ic hiovdd z this input pin has multiple functions. ? for indirect and direct 68, this pin must be connected to hiov dd . ? for indirect and direct 80 type 1 and type 2, this pin is the read enable signal (rd#). ? for indirect and direct 80 type 3, this pin is the db[7:0] lower byte read enable signal (rdl#). we# i h13 ic hiovdd z this input pin has multiple functions. ? for indirect and direct 68, this pin is the read/write signal (r/w#). ? for indirect and direct 80 type 1, this pin is the write enable signal (we#). ? for indirect and direct 80 type 2, this pin must be connected to hiov dd . ? for indirect and direct 80 type 3, this pin is the db[7:0] lower byte write enable signal (wel#). be1# i h12 ic hiovdd z this input pin has multiple functions. ? for indirect and direct 68, this pin is the d[15:8] upper data strobe (uds#). ? for indirect and direct 80 type 1, this pin is the d[15:8] upper byte enable signal (ube#). ? for indirect and direct 80 type 2, this pin is the db[15:8] upper byte write enable signal (weu#). ? for indirect and direct 80 type 3, this pin is the db[15:8] upper byte read enable signal (rdu#). be0# i j11 ic hiovdd z this input pin has multiple functions. ? for indirect and direct 68, this pin is the d[7:0] lower data strobe (lds#). ? for indirect and direct 80 type 1, this pin is the d[7:0] lower byte enable signal (lbe#). ? for indirect and direct 80 type 2, this pin is the db[7:0] lower byte write enable signal (wel#). ? for indirect and direct 80 type 3, this pin is the db[15:8] upper byte write enable signal (weu#). wait# o j13 oln35t hiovdd z during a data transfer, wait# is driven active (low) to force the system to insert wait states. it is driven inactive to indicate the completion of a data transfer. wait# is released to a high impedance state after the data transfer is complete. this pin can be masked using the cnf0 pin. int o k11 oln35 hiovdd l interrupt output. when an internal interrupt occurs, this output pin is driven high. if the host cpu clears the internal interrupt, this pin is driven low. table 5-3: host interface pin descriptions (continued) pin name type fcbga pin# cell power reset# state description free datasheet http:///
page 34 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reset# i j12 ihcs hiovdd z this active low input sets all internal registers to their default state and forces all signals to their inactive states. scs# i k13 icu hiovdd 1 this input pin has multiple functions. ? for serial bypass mode, this pin is the serial chip select input for the host cpu serial interface. when serial bypass mode is enabled, the host cpu can directly control the lcd2 serial interface lcd. ? sclk i l11 icd hiovdd 0 this input pin has multiple functions. ? for serial bypass mode, this pin is the serial clock input for the host cpu serial interface. when serial bypass mode is enabled, the host cpu can directly control the lcd2 serial interface lcd. ? sa0 i k14 icd hiovdd 0 this input pin has multiple functions. ? for serial bypass mode, this pin is the serial a0 command input for the host cpu serial interface. when serial bypass mode is enabled, the host cpu can directly control the lcd2 serial interface lcd. ? si i k12 icd hiovdd 0 this input pin has multiple functions. ? for serial bypass mode, this pin is the serial data input for the host cpu serial interface. when serial bypass mode is enabled, the host cpu can directly control the lcd2 serial interface lcd. ? table 5-3: host interface pin descriptions (continued) pin name type fcbga pin# cell power reset# state description free datasheet http:///
epson research and development page 35 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 5.2.3 lcd interface many of the lcd interface pins have different functions depending on the configured panel interface mode. see table 5-13: ?lcd interface pin mapping,? on page 46 for more details on the pin functions. ? mode 1 is lcd1: rgb, lcd2: serial ? mode 2 is lcd1: parallel, lcd2: serial ? mode 3 is lcd1: parallel, lcd2: parallel ? mode 4 is lcd1: rgb, lcd2: parallel for further information on the three panel interface modes, see the bit description for reg[0032h] bits 1-0. table 5-4: lcd interface pin descriptions pin name type fcbga pin# cell power reset# state description fpdat[17:0] o j1,j4,h3, h2,h4,g1, g4,g2, g4,f1,f2, e4,f3,e2, e1,d1,e3, d2 oln35 piovdd l these output pins have multiple functions. ? for mode 1 and mode 4 rgb interfaces, these pins are the lcd1 rgb data outputs. ? for mode 2, mode 3 and mode 4 parallel interfaces, fpdat[17:0] are the parallel interface data outputs. ? when reg[0056h] bit 13 = 1 or reg[005eh] bit 13 = 1, these pins are controlled with tri-state. ? for parallel bypass mode, these pins output the host cpu data. see table 5-14: ?serial bypass pin mapping,? on page 47. fpframe o d3 oln35 piovdd l (h) this output pin has multiple functions. ? for mode 1 and mode 4 rgb interfaces, this pin is the lcd1 frame pulse output. ? for mode 2, mode 3 and mode 4 parallel interfaces, this pin is the write command output. ? for parallel bypass mode, this pin outputs the host cpu xwr signal. fpline o c1 oln35 piovdd l this output pin has multiple functions. ? for mode 1 and mode 4 rgb interfaces, this pin is the lcd1 line pulse output. ? for mode 2, mode 3 and mode 4 parallel interfaces, this pin is the a0 output. ? for parallel bypass mode, this pin outputs the host cpu a0 signal. fpshift o a3 oln35 piovdd l this output pin has multiple functions. ? for mode 1 and mode 4, this pin is the lcd1 pixel clock output. ? for all other cases, this pin is not used. free datasheet http:///
page 36 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential drdy o c3 oln35 piovdd l this output pin has multiple functions. ? for mode 1 and mode 4, this pin is the lcd1 drdy output. ? for all other cases, this pin is not used. fpcs1# o b3 oln35 piovdd l (h) this output pin has multiple functions. ? for mode 1 and mode 4, this pin is the lcd1 serial interface chip select output. ? for mode 2 and mode 3, this pin is the lcd1 parallel interface chip select output. ? for parallel bypass mode, this pin outputs the host cpu ncs1 signal. fpcs2# o c4 oln35 piovdd l (mode 3 = h) this output pin has multiple functions. ? for mode 1, this pin is the lcd2 serial interface chip select output. when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the scs# pin. ? for mode 2, this pin is the lcd2 serial interface chip select output. when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the scs# pin. ? for mode 3 and 4, this pin is the lcd2 parallel interface chip select output. ? for serial or parallel bypass mode, this pin outputs the host cpu ncs2 signal. fpsclk o a4 oln35 piovdd l this output pin has multiple functions. ? for mode 1, this pin is the lcd1 and lcd2 serial interface clock output. for mode 4, this pin is the lcd1 serial interface clock output. for lcd2, when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the sclk pin. ? for mode 2, this pin is the lcd2 serial interface clock output. when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the sclk pin. ? for mode 3, this pin is not used. ? for serial bypass mode, this pin outputs the host cpu sck signal. table 5-4: lcd interface pin descriptions (continued) pin name type fcbga pin# cell power reset# state description free datasheet http:///
epson research and development page 37 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential fpa0 o d5 oln35 piovdd l this output pin has multiple functions. ? for mode 1, this pin is the lcd1 and lcd2 serial interface a0 output. for mode 4, this pin is the lcd1 serial interface a0 output. for lcd2, when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the sa0 pin. ? for mode 2, this pin is the lcd2 serial interface a0 output. when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the sa0 pin. ? for mode 3, this pin is not used. ? for serial bypass mode, this pin outputs the host cpu a0 signal. fpso o c5 oln35 piovdd l this output pin has multiple functions. ? for mode 1, this pin is the lcd1 and lcd2 serial interface data output. for mode 4, this pin is the lcd1 serial interface data output. for lcd2, when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the si pin. ? for mode 2, this pin is the lcd2 serial interface data output. when power save is enabled or when serial bypass mode is enabled, this pin outputs the state of the si pin. ? for mode 3, this pin is not used. ? for serial bypass mode, this pin outputs the host cpu si signal. fpvin1 i b5 ic piovdd z this input pin has multiple functions. ? for mode 2, mode 3 and mode 4, this pin is the parallel interface lcd1 vertical sync input from the lcd panel. if this pin is not used, it must be connected to ground (vss). fpvin2 i d6 ic piovdd z this input pin has multiple functions. ? for mode 1 and mode 2, this pin is the lcd2 serial interface vertical sync input from the lcd panel. ? for mode 3 and mode 4, this pin is the lcd2 parallel interface vertical sync input from the lcd panel. if this pin is not used, it must be connected to ground (vss). table 5-4: lcd interface pin descriptions (continued) pin name type fcbga pin# cell power reset# state description free datasheet http:///
page 38 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.2.4 camera interface the camera interface supports a type 1, 8-bit bus camera interface. see table 5-16: ?camera interface pin mapping,? on page 48 for details on the connections for the camera interface. note on reset# this output drives low when reset# is low, then drives high once re- set# goes high. table 5-5: camera interface pin descriptions pin name type fcbga pin# cell power reset# state description cmdat[7:0] io l10,m10, n10,p10, p9,m9,n9, l8 blnc35d ciovdd 0 for the camera interface, these pins are the 8- bit data input (camdat[7:0]). cmvref io m8 blnc35d ciovdd 0 for the camera interface, this pin is the vertical sync input (vref). cmhref io n8 blnc35d ciovdd 0 for the camera interface, this pin is the horizontal sync input (href). cmclkout o n7 oln35 ciovdd l for the camera interface, this pin is the master clock output (cammclk). cmclkin io m7 blnc35ds ciovdd 0 for the camera interface, this pin is the camera pixel clock input (campclk). cmstrout o p3 oln35 ciovdd see note this output pin is the camera interface strobe (flash). free datasheet http:///
epson research and development page 39 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 5.2.5 sd memory card interface 5.2.6 clock input table 5-6: sd memory card interface pin descriptions pin name type fcbga pin# cell power reset# state description sddat[3:0] io p6,l6,p5, n5 blnc35d siovdd 0 these input/output pins are the sd memory card data io. sdcmd io p4 blnc35d siovdd 0 this input/output pin is the sd memory card command io. sdclk io m4 blnc35d siovdd 0 this input/output pin is the sd memory card clock output. sdcd# i l5 ihcsd siovdd 0 this input pin is the sd memory card detect. sdwp i m3 ihcsd siovdd 0 this input pin is the sd memory card write protection input. sdgpo o p7 oln35 siovdd l this output pin is the sd memory card general purpose output port. table 5-7: clock input pin descriptions pin name type fcbga pin# cell power reset# state description clki i l12 ilcs hiovdd z this input pin has multiple functions. ? when the internal pll is used, this pin is the input reference clock for the internal pll (32.768khz). ? when the pll is bypassed, this pin is the digital clock input for the system clock (sysclk). free datasheet http:///
page 40 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.2.7 miscellaneous note when cnf1 = 0 (gpio pins are outputs), the reset state of gpio[3:0] is 0. when cnf1 = 1 (gpio pins default to inputs), the reset state of gpio[3:0] is hi-z. table 5-8: miscellaneous pin descriptions pin name type fcbga pin# cell power reset# state description cnf[6:3] i m12,m11, n12,n11 ic ciovdd z these inputs are used for configuring the S1D13717 and must be connected to either ciovdd or vss. the states of these pins are latched at reset#. for more information, see table 5-10: ?summary of power-on/reset options,? on page 42. cnf[2:0] i l2,k3,l1 ic piovdd z these inputs are used for configuring the S1D13717 and must be connected to either piovdd or vss. the states of these pins are latched at reset#. for more information, see table 5-10: ?summary of power-on/reset options,? on page 42. gpio[3:0] io l4,k2,j3, k4 blnc35d piovdd see note these pins are general purpose input/output pins. their default configuration (input or output) is controlled using cnf1. testen i m1 itd piovdd 0 test enable input used for production test only. this pin should be left unconnected for normal operation. scanen i l3 icd piovdd 0 scan enable input used for production test only. this pin should be left unconnected for normal operation. vcp i m14 iltr corevdd ? pll output monitor pin used for production test only. this pin should be left unconnected for normal operation. free datasheet http:///
epson research and development page 41 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 5.2.8 power and ground table 5-9: power and ground pin descriptions pin name type fcbga pin# cell power reset# state description hiovdd p c12, d7, g14 p ? ? io power supply for the host interface piovdd p c2, j2 p ? ? io power supply for the panel interface ciovdd p p11 p ? ? io power supply for the camera interface siovdd p m5, m6 p ? ? io power supply for the sd memory card interface corevdd p a5, a9, e13, f4, l14, m2, p8 p ? ? core power supply vss p b4, c8, d4, d10, d13, f14, h1, j14, k1, l7, l9, n3, n4, n6, p12 p?? gnd for hiovdd, piovdd, ciovdd and corevdd pllvdd p l13 p ? ? pll power supply. this supply should be isolated from the other supplies. pllvss p m13 p ? ? gnd for pllvdd. this ground should be isolated from the other grounds. free datasheet http:///
page 42 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.3 summary of configuration options these pins are used for configuration of the chip and must be connected directly to piovdd or vss. the state of cnf[6:0] are latched on the rising edge of reset#. changing state at any other time has no effect. table 5-10: summary of power-on/reset options configuration input power-on/reset state 1 (cnf[6:3] connected to ciovdd, cnf[2:0] connected to piovdd) 0 (connected to vss) cnf6 2 cs# mode 1 cs# mode cnf5 big endian little endian cnf[4:2] select host bus interface as follows: cnf4 cnf3 cnf2 host bus 0 0 0 direct 80 type 2 0 0 1 direct 80 type 3 0 1 0 indirect 80 type 2 0 1 1 indirect 80 type 3 1 0 0 direct 80 type 1 1 0 1 direct 68 1 1 0 indirect 80 type 1 1 1 1 indirect 68 cnf1 all gpio pins (gpio[3:0]) are configured as inputs. note: when cnf1=1 at reset#, reg[0300h]- reg[0302h] can be used to change individual gpio pins between inputs/outputs. all gpio pins (gpio[3:0] are configured as outputs. note: when cnf1=0 at reset#, reg[0300h]- reg[0302h] are ignored and the gpio pins are always outputs. cnf0 for direct host bus interface types (see cnf[4:2]) wait# is used. the setup/hold time of a[17:1], ube#, lbe# from the rd# edge is not 0 and the setup time of cs# edge from rd# is not 0 (direct 80 types, see section 7.3, ?host interface timing? on page 56 for the signal names for other direct host bus interfaces). note: when wait# is used (cnf0 = 1), wait# may not be asserted for all cycles. wait# is only asserted when needed. wait# is not used. the setup/hold time of a[17:1], ube#, lbe# from the rd# edge is 0 and the setup time of cs# edge from rd# is 0 (direct 80 types, see section 7.3, ?host interface timing? on page 56 for the signal names for other direct host bus interfaces). note: when wait# is not used (cnf0 = 0), wait# is never asserted for any cycles and the host cpu must insert software wait states as needed to guarantee cycle length as outlined in section 7.3.9, ?wait length? on page 88. for indirect host bus interface types (see cnf[4:2]) wait# is not used. the setup/hold time of a[2:1], ube#, lbe# from the rd# edge is not 0 and the setup time of cs# edge from rd# is not 0 (indirect 80 types, see section 7.3, ?host interface timing? on page 56 for the signal names for other indirect host bus interfaces). wait# is not used. the setup/hold time of a[2:1], ube#, lbe# from the rd# edge is 0 and the setup time of cs# edge from rd# is 0 (indirect 80 types, see section 7.3, ?host interface timing? on page 56 for the signal names for other indirect host bus interfaces). free datasheet http:///
epson research and development page 43 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential note when wait# is used (cnf0 = 1), wait# may not be asserted for all cycles. wait# is only asserted when needed. when wait# is not used (cnf0 = 0), wait# is never as- serted for any cycles and the host cpu must insert software wait states as needed to guarantee cycle length as outlined in section 7.3.9, ?wait length? on page 88. free datasheet http:///
page 44 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.4 host interface pin mapping table 5-11: host interface pin mapping (1 cs# mode) pin name direct 68 direct 80 type 1 direct 80 type 2 direct 80 type 3 indirect 68 indirect 80 type 1 indirect 80 type 2 indirect 80 type 3 serial ab[17:2] a[17:2] a[17:2] a[17:2] a[17:2] low ? ab1 a1 a1 a1 a1 a1 a1 a1 a1 ? db[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] ? cs# cs# cs# cs# cs# cs# cs# cs# cs# ? m/r# external decode low ? rd# high rd# rd# rdl# high rd# rd# rdl# ? we# r/w# we# high wel# r/w# we# high wel# ? be#[1] uds# ube# weu# rdu# uds# ube# weu# rdu# ? be#[0] lds# lbe# wel# weu# lds# lbe# wel# weu# ? wait# wait# wait# wait# wait# wait# wait# wait# wait# ? int????????? reset# reset# reset# reset# reset# reset# reset# reset# reset# ? scs#????????cs# sclk???????? serial clock sa0????????a0 si???????? serial data free datasheet http:///
epson research and development page 45 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential table 5-12: host interface pin mapping (2 cs# mode) pin name direct 68 direct 80 type 1 direct 80 type 2 direct 80 type 3 indirect 68 indirect 80 type 1 indirect 80 type 2 indirect 80 type 3 serial ab[17:2] a[17:2] a[17:2] a[17:2] a[17:2] indirect host bus interfaces always function in 1 cs# (cnf6 setting is ignored). see table 5-12: ?host interface pin mapping (2 cs# mode),? on page 45. ?? ab1 a1 a1 a1 a1 ? db[15:0] d[15:0] d[15:0] d[15:0] d[15:0] ? cs# csm# csm# csm# csm# ? m/r# csr# csr# csr# csr# ? rd# high rd# rd# rdl# ? we# r/w# we# high wel# ? be#[1] uds# ube# weu# rdu# ? be#[0] lds# lbe# wel# weu# ? wait# wait# wait# wait# wait# ? int ? ? ? ? ? reset# reset# reset# reset# reset# ? scs# ? ? ? ? cs# sclk???? serial clock sa0 ? ? ? ? a0 si???? serial data free datasheet http:///
page 46 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.5 lcd interface pin mapping table 5-13: lcd interface pin mapping pin name mode 1 mode 2 mode 3 mode 4 lcd1 lcd2 lcd1 lcd2 lcd1 lcd2 lcd1 lcd2 rgb interface serial i/f parallel i/f serial i/f parallel i/f parallel i/f rgb interface parallel i/f general tft nd-tfd a-si tft tft with uwire i/f fpframe vsync vsync vsync vsync xwr xwr xwr see lcd1 for mode 1 xwr fpline hsync hsync hsync hsync a0 a0 a0 a0 fpshift dclk dck dclk clk drdy drdy enab enab fpdat0 r5 r5 d0 d0 d0 d0 fpdat1 r4 r4 r4 r4 d1 d1 d1 d1 fpdat2 r3 r3 r3 r3 d2 d2 d2 d2 fpdat3 g5 g5 g5 g5 d3 d3 d3 d3 fpdat4 g4 g4 g4 g4 d4 d4 d4 d4 fpdat5 g3 g3 g3 g3 d5 d5 d5 d5 fpdat6 b5 b5 d6 d6 d6 d6 fpdat7 b4 b4 b4 b4 d7 d7 d7 d7 fpdat8 b3 b3 b3 b3 d8 d8 d8 d8 fpdat9 r2 r2 r2 r2 d9 d9 d9 d9 fpdat10r1r1r1r1 d10 d10 d10 d10 fpdat11r0r0r0r0 d11 d11 d11 d11 fpdat12g2g2g2g2 d12 d12 d12 d12 fpdat13g1g1g1g1 d13 d13 d13 d13 fpdat14g0g0g0g0 d14 d14 d14 d14 fpdat15b2b2b2b2 d15 d15 d15 d15 fpdat16b1b1b1b1 d16 d16 d16 d16 fpdat17b0b0b0b0 d17 d17 d17 d17 fpcs1# xcs sstb lcdcs ncs1 ncs1 fpcs2# ncs2 ncs2 ncs2 ncs2 fpsclk sck sclk sclk sck sck fpa0 a0 a0 a0 fpso si sdata sdo si si fpvin1 vin1 vin1 fpvin2 vin2 vin2 vin2 vin2 free datasheet http:///
epson research and development page 47 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. rgb refers to the signals used for rgb panels. table 5-14: serial bypass pin mapping lcd i/f mode 1 lcd i/f mode 2 reg[0032h] bits 1-0 00 10 reg[0032h] bit 8 1 0 1 0 lcd1, lcd2 panel types lcd1: rgb lcd2: serial lcd1: parallel (16/18-bit) lcd2: serial pin name type serial bypass bypass disabled serial bypass bypass disabled scs# i scs# scs# sclk i sclk sclk sa0 i sa0 sa0 si i si si fpframe o rgb rgb xwr xwr fpline o rgb rgb a0 a0 fpshift o rgb rgb ?? drdy o rgb rgb ?? fpdat0 o rgb rgb d0 d0 fpdat1 o rgb rgb d1 d1 fpdat2 o rgb rgb d2 d2 fpdat3 o rgb rgb d3 d3 fpdat4 o rgb rgb d4 d4 fpdat5 o rgb rgb d5 d5 fpdat6 o rgb rgb d6 d6 fpdat7 o rgb rgb d7 d7 fpdat8 o rgb rgb d8 d8 fpdat9 o rgb rgb d9 d9 fpdat10 o rgb rgb d10 d10 fpdat11 o rgb rgb d11 d11 fpdat12 o rgb rgb d12 d12 fpdat13 o rgb rgb d13 d13 fpdat14 o rgb rgb d14 d14 fpdat15 o rgb rgb d15 d15 fpdat16 o rgb rgb d16 d16 fpdat17 o rgb rgb d17 d17 fpcs1# o rgb rgb ncs1 ncs1 fpcs2# o ncs2 ncs2 ncs2 ncs2 fpsclk o rgb or sck rgb sck sck fpa0 o rgb or a0 rgb a0 a0 fpso o rgb or si rgb si si fpvin1 i rgb rgb vin1 vin1 fpvin2 i vin2 vin2 vin2 vin2 input port when bypass is used output port when bypass is used when bypass is not used, pull-up/pull-down resistors can be set using reg[0014h] bit 4 table 5-15: lcd interface mode 1/2 bypass endian/data width pin mapping panel mode lcd i/f mode 1 lcd i/f mode 2 serial bypass enabled (reg[0032h] bit 8) 11 input/output input output input output pin mapping scs# fpcs2# scs# fpcs2# sclk fpsclk sclk fpsclk sa0 fpa0 sa0 fpa0 si fpso si fpso free datasheet http:///
page 48 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 5.6 camera interface pin mapping table 5-16: camera interface pin mapping pin name type 1 camera cmdat[7:0] camdat[7:0] cmvref vref cmhref href cmclkout cammclk cmclkin campclk free datasheet http:///
epson research and development page 49 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 6 d.c. characteristics table 6-1: absolute maximum ratings symbol parameter rating units core v dd core supply voltage v ss - 0.3 ~ 2.5 v pll v dd pll supply voltage v ss - 0.3 ~ 2.1 v hio v dd host io supply voltage core v dd ~ 4.0 v pio v dd non-host io supply voltage core v dd ~ 4.0 v cio v dd camera io supply voltage core v dd ~ 4.0 v sio v dd sd card io supply voltage core v dd ~ 4.0 v v in input voltage v ss - 0.3 ~ io v dd + 0.5 v v out output voltage v ss - 0.3 ~ io v dd + 0.5 v table 6-2: recommended operating conditions symbol parameter condition min typ max units core v dd core supply voltage v ss = 0 v 1.65 1.80 1.95 v pll v dd pll supply voltage v ss = 0 v 1.65 1.80 1.95 v hio v dd host io supply voltage v ss = 0 v 2.75 3.00 3.25 v pio v dd non-host io supply voltage v ss = 0 v 2.75 3.00 3.25 v cio v dd camera io supply voltage v ss = 0 v 2.75 3.00 3.25 v sio v dd sd card io supply voltage v ss = 0 v 2.75 3.00 3.25 v v in input voltage v ss hio v dd v v ss pio v dd v ss cio v dd v ss sio v dd t opr operating temperature ? -20 25 70 c free datasheet http:///
page 50 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 6-3: electrical characteristics for vdd = 3.0v typical symbol parameter condition min typ max units i ddsh io quiescent current quiescent conditions 10 a i ddsl core quiescent current quiescent conditions 10 a i iz input leakage current -5 5 a i oz output leakage current -5 5 a hiov oh high level output voltage hiovdd = min i oh = -3.6ma hiov dd - 0.4 v ciov oh high level output voltage ciovdd = min i oh = -3.6ma ciov dd - 0.4 v piov oh high level output voltage piovdd = min i oh = -3.6ma piov dd - 0.4 v siov oh high level output voltage siovdd = min i oh = -3.6ma siov dd - 0.4 v hiov ol low level output voltage hiovdd = min i ol = 3.6ma 0.4 v ciov ol low level output voltage ciovdd = min i ol = 3.6ma 0.4 v piov ol low level output voltage piovdd = min i ol = 3.6ma 0.4 v siov ol low level output voltage siovdd = min i ol = 3.6ma 0.4 v hiov ih high level input voltage lvcmos level, v dd = max 1.95 v ciov ih high level input voltage lvcmos level, v dd = max 1.95 v piov ih high level input voltage lvcmos level, v dd = max 1.95 v siov ih high level input voltage lvcmos level, v dd = max 1.95 v hiov il low level input voltage lvcmos level, v dd = min 0.85 v ciov il low level input voltage lvcmos level, v dd = min 0.85 v piov il low level input voltage lvcmos level, v dd = min 0.85 v siov il low level input voltage lvcmos level, v dd = min 0.85 v hiov t+ positive trigger voltage lvcmos schmitt 1.35 2.5 v ciov t+ positive trigger voltage lvcmos schmitt 1.35 2.5 v piov t+ positive trigger voltage lvcmos schmitt 1.35 2.5 v siov t+ positive trigger voltage lvcmos schmitt 1.35 2.5 v hiov t- negative trigger voltage lvcmos schmitt 0.7 1.6 v ciov t- negative trigger voltage lvcmos schmitt 0.7 1.6 v piov t- negative trigger voltage lvcmos schmitt 0.7 1.6 v siov t- negative trigger voltage lvcmos schmitt 0.7 1.6 v r pd pull down resistance v in = v dd 30 60 144 k r pu pull up resistance v in = v dd 30 60 144 k c i input pin capacitance f = 1mhz, v dd = 0v - - 8 pf c o output pin capacitance f = 1mhz, v dd = 0v - - 8 pf c io bi-directional pin capacitance f = 1mhz, v dd = 0v - - 8 pf free datasheet http:///
epson research and development page 51 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7 a.c. characteristics conditions: io v dd = 3.0v 0.25v t a = -40 c to 85 c t rise and t fall for all inputs except clki must be < 50 ns (10% ~ 90%) c l = 15pf (host interface) c l = 15pf (camera interface) c l = 30pf (lcd panel/gpio interface) c l = 50pf (sd card interface) 7.1 clock timing 7.1.1 input clocks figure 7-1: clock input requirements (pll) 90% 10% v ih v il t pwh t pwl t r t f t osc t cycle 1 t cycle 2 t cjper free datasheet http:///
page 52 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 1. t cjcycle = t cycle 1 - t cycle 2 2. the input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). 3. the input clock cycle jitter is the difference in period between adjacent cycles. 4. the jitter characteristics must satisfy both the t cjper and t cjcycle characteristics. figure 7-2: clock input requirements (pll bypassed) table 7-1: clock input requirements (pll) symbol parameter min typ max units f osc input clock frequency 30 32.768 64 khz t osc input clock period 1/f osc us t pwh input clock pulse width high 5 us t pwl input clock pulse width low 5 us t r input clock rising time (10% - 90%) 5 us t f input clock falling time (10% - 90%) 5 us t cjper input clock period jitter (see notes 2 and 4) -100 100 ns t cjcycle (see note 1) input clock cycle jitter (see notes 3 and 4) -100 100 ns table 7-2: clock input requirements (pll bypassed) symbol parameter min max units f osc input clock frequency (clki) 55 mhz t osc input clock period (clki) 1/f osc ns t pwh input clock pulse width high (clki) 0.4t osc ns t pwl input clock pulse width low (clki) 0.4t osc ns t r input clock rising time (10% - 90%) 5 ns t f input clock falling time (10% - 90%) 5 ns t pwl t pwh t f clock input waveform t r t osc v ih v il 10% 90% free datasheet http:///
epson research and development page 53 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.1.2 pll clock the pll circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. noise on the clock or the supplied power may cause the operation of the pll circuit to become unstable or increase the jitter. due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the pll be isolated from those of other power supplies. filtering should also be used to keep the power as clean as possible. the jitter of the input clock waveform should be as small as possible. for example, if noise with a 2khz frequency modulation is added on pllvdd, the jitter on the pll clock output may fluctuate. measures must be taken to avoid noise within the range of 1khz to 3khz. the specific design should be confirmed to determine the jitter value of a clock. this is because the actual jitter characteristics are affected by a combination of factors, such as the jitter frequency spectrum of clki, and amplitude and frequency of the noise on the supplied power. if the jitter of a clock exceeds the requirement of a module, an external oscillator should be used instead of using the internal pll circuitry. free datasheet http:///
page 54 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-3: pll start-up time 7.1.3 internal clocks table 7-3: internal clock requirements symbol parameter min max units f sys internal clock frequency (system clock) 55 mhz 32khz pll xxmhz output (xx = 40-55mhz) 100 ms note: pll minimum frequency = 40mhz pll maximum frequency = 55mhz the pll frequency will ramp between the off state and the programmed frequency. to guarantee the lowest possible clock jitter, 100ms is required for stabilization. jitter (ns) time (ms) specification (2%) pll enable lock in time lock in time reference clock 100 ms pll stable free datasheet http:///
epson research and development page 55 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.2 power supply sequence 7.2.1 power-on sequence figure 7-4: power-on sequence 7.2.2 power-off sequence figure 7-5: power-off sequence table 7-4: power-on sequence symbol parameter min max units t1 iov dd on delay from corev dd / pllv dd on 0 ns t2 reset# width period 1 clki table 7-5: power-off sequence symbol parameter min max units t1 corev dd / pllv dd off delay from iov dd off 0 ns corev dd hiov dd piov dd ciov dd t1 reset# t2 pllv dd siov dd corev dd hiov dd piov dd ciov dd t1 pllv dd siov dd free datasheet http:///
page 56 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3 host interface timing 7.3.1 direct 80 type 1 figure 7-6: direct 80 type 1 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t0109min = wait length + 3 ts. table 7-6: direct 80 type 1 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t0101 cs# setup time 15 ns t0102 a[17:1], m/r#, ube#, lbe# setup time 15 ns t0103 we# falling edge to wait# driven low 10 ns t0104 d[15:0] setup time to we# rising edge 10 ns t0105 cs# hold time from we# rising edge 5 ns t0106 a[17:1], m/r#, ube#, lbe# hold time from we# rising edge 5 ns t0107 we# rising edge to wait# high impedance 7 ns t0108 d[15:0] hold time from we# rising edge 2 ns t0109 cycle time (no wait mode only) note2,3 ts cs# we# wait# valid d[15:0] t0101 t0102 t0103 t0105 t0106 t0107 t0108 (write) t0104 t0109 a[17:1] m/r# ube#, lbe# (no wait mode: hi-z) free datasheet http:///
epson research and development page 57 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-7: direct 80 type 1 interface read cycle timing (wait mode) table 7-7: direct 80 type 1 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t0121 cs# setup time 15 ns t0122 a[17:1], m/r#, ube#, lbe# setup time 15 ns t0123 rd# falling edge to wait# driven low 10 ns t0124 rd# falling edge to d[15:0] driven 4 ns t0125 cs# hold time from rd# rising edge 2 ns t0126 a[17:1], m/r#, ube#, lbe# hold time from rd# rising edge 2 ns t0127 rd# rising edge to wait# high impedance 7 ns t0128 d[15:0] hold time from rd# rising edge. 2 8 ns t0129 wait# rising edge to valid data if wait# is asserted 10 ns t0130 rd# falling edge to valid data if wait# is not asserted 17 ns cs# a[17:1] rd# wait# valid d[15:0] t0121 t0122 t0123 t0124 t0125 t0126 t0127 t0128 (read) m/r# ube#, lbe# t0129 t0130 free datasheet http:///
page 58 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-8: direct 80 type 1 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t0147max = wait length + 29 ns table 7-8: direct 80 type 1 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t0141 cs# setup time 0 ns t0142 a[17:1], m/r#, ube#, lbe# setup time 0 ns t0143 rd# falling edge to d[15:0] driven 4 ns t0144 cs# hold time from rd# rising edge 0 ns t0145 a[17:1], m/r#, ube#, lbe# hold time from rd# rising edge 0 ns t0146 d[15:0] hold time from rd# rising edge 2 8 ns t0147 rd# falling edge to valid data if there are no internal delayed cycles note1,2 ns t0148 rd# pulse width high 10 ns cs# a[17:1] rd# valid d[15:0] t0141 t0143 t0144 t0145 t0146 (read) m/r# ube#, lbe# t0147 t0148 t0142 t0148 free datasheet http:///
epson research and development page 59 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-9: direct 80 type 1 host interface truth table for little endian we# rd# ube# lbe# d[15:8] d[7:0] comments 0100validvalid16-bit write 0110 -valid8-bit write; data on low byte (even byte address 1 ) 0101valid-8-bit write; data on high byte (odd byte address 1 ) 1000validvalid16-bit read 1010 -valid8-bit read; data on low byte (even byte address 1 ) 1001valid-8-bit read; data on high byte (odd byte address 1 ) table 7-10: direct 80 type 1 host interface truth table for big endian we# rd# ube# lbe# d[15:8] d[7:0] comments 0100validvalid16-bit write 0110 -valid8-bit write; data on low byte (odd byte address 1 ) 0101valid-8-bit write; data on high byte (even byte address 1 ) 1000validvalid16-bit read 1010 -valid8-bit read; data on low byte (odd byte address 1 ) 1001valid-8-bit read; data on high byte (even byte address 1 ) free datasheet http:///
page 60 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.2 direct 80 type 2 figure 7-9: direct 80 type 2 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t0209min = wait length + 3 ts table 7-11: direct 80 type 2 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t0201 cs# setup time 15 ns t0202 a[17:1], m/r# setup time 15 ns t0203 weu#,wel# falling edge to wait# driven low 10 ns t0204 d[15:0] setup time to weu#,wel# rising edge 10 ns t0205 cs# hold time from weu#,wel# rising edge 5 ns t0206 a[17:1], m/r# hold time from weu#,wel# rising edge 5 ns t0207 weu#,wel# rising edge to wait# high impedance 7 ns t0208 d[15:0] hold time from weu#,wel# rising edge 2 ns t0209 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t0201 t0202 t0203 t0205 t0206 t0207 t0208 (write) t0204 t0209 a[17:1] m/r# weu#,wel# (no wait mode: hi-z) free datasheet http:///
epson research and development page 61 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-10: direct 80 type 2 interface read cycle timing (wait mode) table 7-12: direct 80 type 2 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t0221 cs# setup time 15 ns t0222 a[17:1], m/r# setup time 15 ns t0223 rd# falling edge to wait# driven low 10 ns t0224 rd# falling edge to d[15:0] driven 4 ns t0225 cs# hold time from rd# rising edge 2 ns t0226 a[17:1], m/r# hold time from rd# rising edge 2 ns t0227 rd# rising edge to wait# high impedance 7 ns t0228 d[15:0] hold time from rd# rising edge. 2 8 ns t0229 wait# rising edge to valid data if wait# is asserted 10 ns t0230 rd# falling edge to valid data if wait# is not asserted 17 ns cs# a[17:1] rd# wait# valid d[15:0] t0221 t0222 t0223 t0224 t0225 t0226 t0227 t0228 (read) m/r# t0229 t0230 free datasheet http:///
page 62 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-11: direct 80 type 2 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t0247max = wait length + 29 ns table 7-13: direct 80 type 2 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t0241 cs# setup time 0 ns t0242 a[17:1], m/r# setup time 0 ns t0243 rd# falling edge to d[15:0] driven 4 ns t0244 cs# hold time from rd# rising edge 0 ns t0245 a[17:1], m/r# hold time from rd# rising edge 0 ns t0246 d[15:0] hold time from rd# rising edge 2 8 ns t0247 rd# falling edge to valid data if there are no internal delayed cycles note1,2 ns t0248 rd# pulse width high 10 ns cs# a[17:1] rd# valid d[15:0] t0241 t0242 t0243 t0244 t0245 t0246 (read) m/r# t0247 t0248 t0248 free datasheet http:///
epson research and development page 63 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-14: direct 80 type 2 host interface truth table for little endian rd# weu# wel# d[15:8] d[7:0] comments 1 0 0 valid valid 16-bit write 1 1 0 - valid 8-bit write; data on low byte (even byte address 1 ) 1 0 1 valid - 8-bit write; data on high byte (odd byte address 1 ) 0 1 1 valid valid 16-bit read free datasheet http:///
page 64 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.3 direct 80 type 3 figure 7-12: direct 80 type 3 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t0309min = wait length + 3 ts table 7-15: direct 80 type 3 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t0301 cs# setup time 15 ns t0302 a[17:1], m/r# setup time 15 ns t0303 weu#,wel# falling edge to wait# driven low 10 ns t0304 d[15:0] setup time to weu#,wel# rising edge 10 ns t0305 cs# hold time from weu#,wel# rising edge 5 ns t0306 a[17:1], m/r# hold time from weu#,wel# rising edge 5 ns t0307 weu#,wel# rising edge to wait# high impedance 7 ns t0308 d[15:0] hold time from weu#,wel# rising edge 2 ns t0309 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t0301 t0302 t0303 t0305 t0306 t0307 t0308 (write) t0304 t0309 a[17:1] weu#,wel# m/r# (no wait mode: hi-z) free datasheet http:///
epson research and development page 65 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-13: direct 80 type 3 interface read cycle timing (wait mode) table 7-16: direct 80 type 3 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t0321 cs# setup time 15 ns t0322 a[17:1], m/r# setup time 15 ns t0323 rdu#,rdl# falling edge to wait# driven low 10 ns t0324 rdu#,rdl# falling edge to d[15:0] driven 4 ns t0325 cs# hold time from rdu#,rdl# rising edge 2 ns t0326 a[17:1], m/r# hold time from rdu#,rdl# rising edge 2 ns t0327 rdu#,rdl# rising edge to wait# high impedance 7 ns t0328 d[15:0] hold time from rdu#,rdl# rising edge. 2 8 ns t0329 wait# rising edge to valid data if wait# is asserted 10 ns t0330 rdu#,rdl# falling edge to valid data if wait# is not asserted 17 ns cs# a[17:1] rdu#,rdl# wait# valid d[15:0] t0321 t0322 t0323 t0324 t0325 t0326 t0327 t0328 (read) m/r# t0329 t0330 free datasheet http:///
page 66 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-14: direct 80 type 3 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88 . 2. t0347max = wait length + 29 ns table 7-17: direct 80 type 3 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t0341 cs# setup time 0 ns t0342 a[17:1], m/r# setup time 0 ns t0343 rdu#,rdl# falling edge to d[15:0] driven 4 ns t0344 cs# hold time from rdu#,rdl# rising edge 0 ns t0345 a[17:1], m/r# hold time from rdu#,rdl# rising edge 0 ns t0346 d[15:0] hold time from rdu#,rdl# rising edge 2 8 ns t0347 rdu#,rdl# falling edge to valid data if there are no internal delayed cycles note1,2 ns t0348 rdu#, rdl# pulse width high 10 ns cs# a[17:1] rdu#,rdl# valid d[15:0] t0341 t0342 t0343 t0344 t0345 t0346 (read) m/r# t0347 t0348 t0348 free datasheet http:///
epson research and development page 67 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-18: direct 80 type 3 host interface truth table for little endian weu# wel# rdu# rdl# d[15:8] d[7:0] comments 0011validvalid16-bit write 1011 -valid8-bit write; data on low byte (even byte address 1 ) 0111valid-8-bit write; data on high byte (odd byte address 1 ) 1100validvalid16-bit read 1110 -valid8-bit read; data on low byte (even byte address 1 ) 1101valid-8-bit read; data on high byte (odd byte address 1 ) table 7-19: direct 80 type 3 host interface truth table for big endian weu# wel# rdu# rdl# d[15:8] d[7:0] comments 0011validvalid16-bit write 1011 -valid8-bit write; data on low byte (odd byte address 1 ) 0111valid-8-bit write; data on high byte (even byte address 1 ) 1100validvalid16-bit read 1110 -valid8-bit read; data on low byte (odd byte address 1 ) 1101valid-8-bit read; data on high byte (even byte address 1 ) free datasheet http:///
page 68 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.4 direct 68 figure 7-15: direct 68 interface write cycle timing (wait/no wait mode) 1. ts = system clock period 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t0409min = wait length + 3 ts table 7-20: direct 68 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t0401 cs# setup time 15 ns t0402 a[17:1], r/w#, m/r# setup time 15 ns t0403 uds#, lds# falling edge to wait# driven low 10 ns t0404 d[15:0] setup time to uds#, lds# rising edge 10 ns t0405 cs# hold time from uds#, lds# rising edge 5 ns t0406 a[17:1], r/w#, m/r# hold time from uds#, lds# rising edge 5 ns t0407 uds#, lds# rising edge to wait# high impedance 7 ns t0408 d[15:0] hold time from uds#, lds# rising edge 2 ns t0409 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t0401 t0402 t0403 t0405 t0406 t0407 t0408 (write) t0404 t0409 a[17:1] uds#, lds# r/w# m/r# (no wait mode: hi-z) free datasheet http:///
epson research and development page 69 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-16: direct 68 interface read cycle timing (wait mode) table 7-21: direct 68 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t0421 cs# setup time 15 ns t0422 a[17:1], r/w#, m/r# setup time 15 ns t0423 uds#, lds# falling edge to wait# driven low 10 ns t0424 uds#, lds# falling edge to d[15:0] driven 4 ns t0425 cs# hold time from uds#, lds# rising edge 2 ns t0426 a[17:1], r/w#, m/r# hold time from uds#, lds# rising edge 2 ns t0427 uds#, lds# rising edge to wait# high impedance 7 ns t0428 d[15:0] hold time from uds#, lds# rising edge 2 8 ns t0429 wait# rising edge to valid data if wait# is asserted 10 ns t0430 uds#, lds# falling edge to valid data if wait# is not asserted 17 ns cs# a[17:1] uds#, lds# r/w# wait# t0421 t0422 t0423 t0425 t0426 t0427 m/r# valid d[15:0] t0424 t0429 t0428 (read) t0430 free datasheet http:///
page 70 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-17: direct 68 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t0447max = wait length + 29 ns table 7-22: direct 68 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t0441 cs# setup time 0 ns t0442 a[17:1], m/r# setup time 0 ns t0443 uds#, lds# falling edge to d[15:0] driven 4 ns t0444 cs# hold time from uds#, lds# rising edge 0 ns t0445 a[17:1], m/r# hold time from uds#, lds# rising edge 0 ns t0446 d[15:0] hold time from uds#, lds# rising edge 2 8 ns t0447 uds#, lds# falling edge to valid data if there are no internal delayed cycles note1,2 ns t0448 uds#, lds# pulse width high 10 ns t0449 r/w# setup time 5 ns t0450 r/w# hold time from uds#, lds# rising edge 2 ns uds#, lds# r/w# t0442 t0449 t0445 t0450 t0443 t0446 valid t0447 d[15:0] (read) cs# a[17:1] m/r# t0441 t0444 t0448 t0448 free datasheet http:///
epson research and development page 71 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-23: direct 68 host interface truth table for little endian r/w# uds# lds# d[15:8] d[7:0] comments 0 0 0 valid valid 16-bit write 0 1 0 - valid 8-bit write; data on low byte (even byte address 1 ) 0 0 1 valid - 8-bit write; data on high byte (odd byte address 1 ) 1 0 0 valid valid 16-bit read 1 1 0 - valid 8-bit read; data on low byte (even byte address 1 ) 1 0 1 valid - 8-bit read; data on high byte (odd byte address 1 ) free datasheet http:///
page 72 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.5 indirect 80 type 1 figure 7-18: indirect 80 type 1 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t1109min = wait length + 3 ts table 7-24: indirect 80 type 1 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t1101 cs# setup time 15 ns t1102 a1, ube#, lbe# setup time 15 ns t1103 we# falling edge to wait# driven low 10 ns t1104 d[15:0] setup time to we# rising edge 10 ns t1105 cs# hold time from we# rising edge 5 ns t1106 a1, ube#, lbe# hold time from we# rising edge 5 ns t1107 we# rising edge to wait# high impedance 7 ns t1108 d[15:0] hold time from we# rising edge 2 ns t1109 cycle time (no wait mode only) note2,3 ts cs# we# wait# valid d[15:0] t1101 t1102 t1103 t1105 t1106 t1107 t1108 (write) a1 ube#, lbe# t1104 t1109 (no wait mode: hi-z) free datasheet http:///
epson research and development page 73 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-19: indirect 80 type 1 interface read cycle timing (wait mode) table 7-25: indirect 80 type 1 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t1121 cs# setup time 15 ns t1122 a1, ube#, lbe# setup time 15 ns t1123 rd# falling edge to wait# driven low 10 ns t1124 rd# falling edge to d[15:0] driven 4 ns t1125 cs# hold time from rd# rising edge 2 ns t1126 a1, ube#, lbe# hold time from rd# rising edge 2 ns t1127 rd# rising edge to wait# high impedance 7 ns t1128 d[15:0] hold time from rd# rising edge. 2 8 ns t1129 wait# rising edge to valid data if wait# is asserted 10 ns t1130 rd# falling edge to valid data if wait# is not asserted 17 ns cs# rd# wait# valid d[15:0] t1121 t1122 t1123 t1124 t1125 t1126 t1127 t1128 (read) a1 ube#, lbe# t1129 t1130 free datasheet http:///
page 74 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-20: indirect 80 type 1 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t1147max = wait length + 29 ns table 7-26: indirect 80 type 1 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t1141 cs# setup time 0 ns t1142 a1, ube#, lbe# setup time 0 ns t1143 rd# falling edge to d[15:0] driven 4 ns t1144 cs# hold time from rd# rising edge 0 ns t1145 a1, ube#, lbe# hold time from rd# rising edge 0 ns t1146 d[15:0] hold time from rd# rising edge 2 8 ns t1147 rd# falling edge to valid data if there are no internal delayed cycles note1,2 ns t1148 rd# pulse width high 10 ns cs# rd# valid d[15:0] t1141 t1142 t1143 t1144 t1145 t1146 (read) a1 ube#, lbe# t1147 t1148 t1148 free datasheet http:///
epson research and development page 75 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-27: indirect 80 type 1 host interface truth table for little endian we# rd# ube# lbe# d[15:8] d[7:0] comments 0100validvalid16-bit command write or data write 0110 -valid 8-bit data write (memory); data on low byte (even byte address 1 ) 0101valid- 8-bit data write (memory); data on high byte (odd byte address 1 ) 1000validvalid16-bit data read 1010 -valid 8-bit data read (memory); data on low byte (even byte address 1 ) 1001valid- 8-bit data read (memory); data on high byte (odd byte address 1 ) table 7-28: indirect 80 type 1 host interface truth table for big endian we# rd# ube# lbe# d[15:8] d[7:0] comments 0100validvalid16-bit command write or data write 0110 -valid 8-bit data write (memory); data on low byte (odd byte address 1 ) 0101valid- 8-bit data write (memory); data on high byte (even byte address 1 ) 1000validvalid16-bit data read 1010 -valid 8-bit data read (memory); data on low byte (odd byte address 1 ) 1001valid- 8-bit data read (memory); data on high byte (even byte address 1 ) table 7-29: indirect 80 type 1 host interface function selection a1 we# rd# comments 0 0 1 16-bit command write (register address) 1 0 1 data write (16-bit register data or 8/16-bit memory data) 1 1 0 data read (16-bit register data or 8/16-bit memory data) free datasheet http:///
page 76 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.6 indirect 80 type 2 figure 7-21: indirect 80 type 2 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t1209min = wait length + 3 ts table 7-30: indirect 80 type 2 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t1201 cs# setup time 15 ns t1202 a1 setup time 15 ns t1203 weu#,wel# falling edge to wait# driven low 10 ns t1204 d[15:0] setup time to weu#,wel# rising edge 10 ns t1205 cs# hold time from weu#,wel# rising edge 5 ns t1206 a1 hold time from weu#,wel# rising edge 5 ns t1207 weu#,wel# rising edge to wait# high impedance 7 ns t1208 d[15:0] hold time from weu#,wel# rising edge 2 ns t1209 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t1201 t1202 t1203 t1205 t1206 t1207 t1208 (write) t1204 t1209 a1 weu#,wel# (no wait mode: hi-z) free datasheet http:///
epson research and development page 77 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-22: indirect 80 type 2 interface read cycle timing (wait mode) table 7-31: indirect 80 type 2 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t1221 cs# setup time 15 ns t1222 a1 setup time 15 ns t1223 rd# falling edge to wait# driven low 10 ns t1224 rd# falling edge to d[15:0] driven 4 ns t1225 cs# hold time from rd# rising edge 2 ns t1226 a1 hold time from rd# rising edge 2 ns t1227 rd# rising edge to wait# high impedance 7 ns t1228 d[15:0] hold time from rd# rising edge. 2 8 ns t1229 wait# rising edge to valid data if wait# is asserted 10 ns t1230 rd# falling edge to valid data if wait# is not asserted 17 ns cs# rd# wait# valid d[15:0] t1221 t1222 t1223 t1224 t1225 t1226 t1227 t1228 (read) a1 t1229 t1230 free datasheet http:///
page 78 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-23: indirect 80 type 2 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t1247max = wait length + 29 ns table 7-32: indirect 80 type 2 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t1241 cs# setup time 0 ns t1242 a1 setup time 0 ns t1243 rd# falling edge to d[15:0] driven 4 ns t1244 cs# hold time from rd# rising edge 0 ns t1245 a1 hold time from rd# rising edge 0 ns t1246 d[15:0] hold time from rd# rising edge 2 8 ns t1247 rd# falling edge to valid data if there are no internal delayed cycles note1,2 ns t1248 rd# pulse width high 10 ns cs# a1 rd# valid d[15:0] t1241 t1242 t1243 t1244 t1245 t1246 (read) t1247 t1248 t1248 free datasheet http:///
epson research and development page 79 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-33: indirect 80 type 2 host interface truth table for little endian rd# weu# wel# d[15:8] d[7:0] comments 1 0 0 valid valid 16-bit command write or data write 1 1 0 - valid 8-bit data write (memory); data on high byte (odd byte address 1 ) 1 0 1 valid - 8-bit data write (memory); data on high byte (even byte address 1 ) 0 1 1 valid valid 16-bit data read table 7-34: indirect 80 type 2 host interface function selection a1 weu#/wel# rd# comments 0 0 1 16-bit command write (register address) 1 0 1 data write (16-bit register data or 8/16-bit memory data) 1 1 0 data read (16-bit register data or 16-bit memory data) free datasheet http:///
page 80 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.7 indirect 80 type 3 figure 7-24: indirect 80 type 3 interface write cycle timing (wait/no wait mode) 1. ts = system clock period. 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t1309min = wait length + 3 ts table 7-35: indirect 80 type 3 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t1301 cs# setup time 15 ns t1302 a1 setup time 15 ns t1303 weu#,wel# falling edge to wait# driven low 10 ns t1304 d[15:0] setup time to weu#,wel# rising edge 10 ns t1305 cs# hold time from weu#,wel# rising edge 5 ns t1306 a1 hold time from weu#,wel# rising edge 5 ns t1307 weu#,wel# rising edge to wait# high impedance 7 ns t1308 d[15:0] hold time from weu#,wel# rising edge 2 ns t1309 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t1301 t1302 t1303 t1305 t1306 t1307 t1308 (write) t1304 t1309 a1 weu#,wel# (no wait mode: hi-z) free datasheet http:///
epson research and development page 81 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-25: indirect 80 type 3 interface read cycle timing (wait mode) table 7-36: indirect 80 type 3 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t1321 cs# setup time 15 ns t1322 a1 setup time 15 ns t1323 rdu#,rdl# falling edge to wait# driven low 10 ns t1324 rdu#,rdl# falling edge to d[15:0] driven 4 ns t1325 cs# hold time from rdu#,rdl# rising edge 2 ns t1326 a1 hold time from rdu#,rdl# rising edge 2 ns t1327 rdu#,rdl# rising edge to wait# high impedance 7 ns t1328 d[15:0] hold time from rdu#,rdl# rising edge. 2 8 ns t1329 wait# rising edge to valid data if wait# is asserted 10 ns t1330 rdu#,rdl# falling edge to valid data if wait# is not asserted 17 ns cs# a1 rdu#,rdl# wait# valid d[15:0] t1321 t1322 t1323 t1324 t1325 t1326 t1327 t1328 (read) t1329 t1330 free datasheet http:///
page 82 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-26: indirect 80 type 3 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88 . 2. t1347max = wait length + 40 ns table 7-37: indirect 80 type 3 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t1341 cs# setup time 0 ns t1342 a1 setup time 0 ns t1343 rdu#,rdl# falling edge to d[15:0] driven 4 ns t1344 cs# hold time from rdu#,rdl# rising edge 0 ns t1345 a1 hold time from rdu#,rdl# rising edge 0 ns t1346 d[15:0] hold time from rdu#,rdl# rising edge 2 8 ns t1347 rdu#,rdl# falling edge to valid data if there are no internal delayed cycles note1,2 ns t1348 rdu#, rdl# pulse width high 10 ns cs# a1 rdu#,rdl# valid d[15:0] t1343 t1346 (read) t1347 t1342 t1345 t1348 t1348 t1341 t1344 free datasheet http:///
epson research and development page 83 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-38: indirect 80 type 3 host interface truth table for little endian weu# wel# rdu# rdl# d[15:8] d[7:0] comments 0011validvalid16-bit command write or data write 1011 -valid 8-bit data write (memory); data on low byte (even byte address 1 ) 0111valid- 8-bit data write (memory); data on high byte (odd byte address 1 ) 1100validvalid16-bit data read 1110 -valid 8-bit data read (memory); data on low byte (even byte address 1 ) 1101valid- 8-bit data read (memory); data on high byte (odd byte address 1 ) table 7-39: indirect 80 type 3 host interface truth table for big endian weu# wel# rdu# rdl# d[15:8] d[7:0] comments 0011validvalid16-bit command write or data write 1011 -valid 8-bit data write (memory); data on low byte (odd byte address 1 ) 0111valid- 8-bit data write (memory); data on high byte (even byte address 1 ) 1100validvalid16-bit data read 1110 -valid 8-bit data read (memory); data on low byte (odd byte address 1 ) 1101valid- 8-bit data read (memory); data on high byte (even byte address 1 ) table 7-40: indirect 80 type 3 host interface function select a1 weu# / wel# rdu# / rdl# comments 0 0 1 16-bit command write (register address) 1 0 1 data write (16-bit register data or 8/16-bit memory data) 1 1 0 data read (16-bit register data or 8/16-bit memory data) free datasheet http:///
page 84 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.8 indirect 68 figure 7-27: indirect 68 interface write cycle timing (wait/no wait mode) 1. ts = system clock period 2. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 3. t1409min = wait length + 3 ts table 7-41: indirect 68 interface write cycle timing (wait/no wait mode) symbol parameter 3.0 volt units min max t1401 cs# setup time 15 ns t1402 a1, r/w# setup time 15 ns t1403 uds#, lds# falling edge to wait# driven low 10 ns t1404 d[15:0] setup time to uds#, lds# rising edge 10 ns t1405 cs# hold time from uds#, lds# rising edge 5 ns t1406 a1, r/w# hold time from uds#, lds# rising edge 5 ns t1407 uds#, lds# rising edge to wait# high impedance 7 ns t1408 d[15:0] hold time from uds#, lds# rising edge 2 ns t1409 cycle time (no wait mode only) note2,3 ts cs# wait# valid d[15:0] t1401 t1402 t1403 t1405 t1406 t1407 t1408 (write) t1404 t1409 uds#, lds# a1 r/w# (no wait mode: hi-z) free datasheet http:///
epson research and development page 85 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 7-28: indirect 68 interface read cycle timing (wait mode) table 7-42: indirect 68 interface read cycle timing (wait mode) symbol parameter 3.0 volt units min max t1421 cs# setup time 15 ns t1422 a1, r/w# setup time 15 ns t1423 uds#, lds# falling edge to wait# driven low 10 ns t1424 uds#, lds# falling edge to d[15:0] driven 4 ns t1425 cs# hold time from uds#, lds# rising edge 2 ns t1426 a1, r/w# hold time from uds#, lds# rising edge 2 ns t1427 uds#, lds# rising edge to wait# high impedance 7 ns t1428 d[15:0] hold time from uds#, lds# rising edge 2 8 ns t1429 wait# rising edge to valid data if wait# is asserted 10 ns t1430 uds#, lds# falling edge to valid data if wait# is not asserted 17 ns cs# a1 uds#, lds# r/w# wait# t1421 t1422 t1423 t1425 t1426 t1427 valid d[15:0] t1424 t1429 t1428 (read) t1430 free datasheet http:///
page 86 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 7-29: indirect 68 interface read cycle timing (no wait mode) 1. when no wait mode is selected, the same wait length cycles must be maintained as when wait mode is selected. see section 7.3.9, ?wait length? on page 88. 2. t1447max = wait length + 29 ns table 7-43: indirect 68 interface read cycle timing (no wait mode) symbol parameter 3.0 volt units min max t1441 cs# setup time 0 ns t1442 a1 setup time 0 ns t1443 uds#, lds# falling edge to d[15:0] driven 4 ns t1444 cs# hold time from uds#, lds# rising edge 0 ns t1445 a1 hold time from uds#, lds# rising edge 0 ns t1446 d[15:0] hold time from uds#, lds# rising edge 2 8 ns t1447 uds#, lds# falling edge to valid data if there are no internal delayed cycles note1,2 ns t1448 uds#, lds# pulse width high 10 ns t1449 r/w# setup time 5 ns t1450 r/w# hold time from uds#, lds# rising edge 2 ns a1 uds#, lds# t1449 t1445 t1450 t1443 t1447 t1446 t1441 t1442 t1444 cs# r/w# t1448 t1448 free datasheet http:///
epson research and development page 87 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. because a0 is not used, all addresses are seen by the S1D13717 as even addresses (16-bit word address aligned on even byte addresses). table 7-44: indirect 68 host interface truth table for little endian r/w# uds# lds# d[15:8] d[7:0] comments 0 0 0 valid valid 16-bit command write or data write 0 1 0 - valid 8-bit data write (memory); data on low byte (even byte address 1 ) 0 0 1 valid - 8-bit data write (memory); data on high byte (odd byte address 1 ) 1 0 0 valid valid 16-bit data read 1 1 0 - valid 8-bit data read (memory); data on low byte (even byte address 1 ) 1 0 1 valid - 8-bit data read (memory); data on high byte (odd byte address 1 ) table 7-45: indirect 68 host interface function select a1 r/w# comments 0 0 16-bit command write (register address) 1 0 data write (16-bit register data or 8/16-bit memory data) 1 1 data read (16-bit register data or 8/16-bit memory data) free datasheet http:///
page 88 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.3.9 wait length the host cpu interfaces of the S1D13717 are asynchronous. however, the cpu signals are latched internally, synchronous to the system clock. the following table shows the wait# length based on the system clock. in the table, ?single? access means there is enough idle time between accesses. the minimum idle time to guarantee a single access is six system clocks from the rising edge of we# of the current access to the rising edge of we# of the next access. ?continuous? access means there is not enough idle time between accesses. if host cpu cycles are assumed to be a minimum of x clocks in length, the actual cycle length will be ? x + the value in the following table?. 1. ts = system clock period 2. memory arbitration (camera and jpeg modules are enabled) 3. no memory arbitration (camera and jpeg modules are disabled) 4. these are typical values. actual wait lengths may be larger than specified when multiple blocks of the S1D13717 are enabled. table 7-46: wait length description min typ (note 4) max unit single write to the registers, except the jpeg codec registers 0 ts (note1) continuous write to the registers, except the jpeg codec registers 5 ts single write to the jpeg codec registers 0 ts continuous write to the jpeg codec registers 4 (note 3) 6 (note 2) ts single write to the display buffer 0 ts continuous write to the display buffer 4 ts single write to the jpeg fifo (reg09a6h) 0 ts continuous write to the jpeg fifo (reg09a6h) 5 ts single/continuous read from the registers, except the jpeg codec registers 5ts read from the registers after a write, except the jpeg codec registers 8 ts single/continuous read from the jpeg codec registers, except the jpeg codec table registers 5 (note 3) 7 (note 2) ts read from the jpeg codec registers after a write, except the jpeg codec table registers 8 (note 3) 10 (note 2) ts single/continuous read from the display buffer 5 ts read from the display buffer after a write 7 ts 1st access of a jpeg fifo continuous read 4 ts last 2 accesses of a jpeg fifo continuous read 4 ts accesses of jpeg fifo continuous read, except above 0 ts free datasheet http:///
epson research and development page 89 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.4 panel interface timing 7.4.1 generic tft panel timing figure 7-30: generic tft panel timing 1. the following formulas must be valid for all panel timings: hdps + hdp < ht vdps + vdp < vt 2. for generic tft panel types, the hpp value must be programmed to 1 and the vpp value must be programmed to 0. these values may be used to configure extended tft types as required. table 7-47: generic tft panel timing symbol description derived from units ht lcd1 horizontal total ((reg[0040h] bits 6-0) + 1) x 8 ts hdp lcd1 display period ((reg[0042h] bits 9-1) + 1) x 2 hdps lcd1 horizontal display period start position ((reg[0044h] bits 9-0) + 9 hpw lcd1 fpline pulse width (reg[0046h] bits 6-0) + 1 hpp lcd1 fpline pulse position (see note 2) (reg[0048h] bits 9-0) + 1 vt lcd1 vertical total (reg[004ah] bits 9-0) + 1 lines vdp lcd1 vertical display peri od (reg[004ch] bits 9-0) + 1 vdps lcd1 vertical display period start position reg[004eh] bits 9-0 vpw lcd1 fpframe pulse width (reg[50h] bits 2-0) + 1 vpp lcd1 fpframe pulse position (see note 2) reg[0052h] bits 9-0 ht vdp vt vdps vpw hdp hpw hdps hpp vpp free datasheet http:///
page 90 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential generic rgb type interface panel horizontal timing figure 7-31: generic rgb type interface panel horizontal timing 1. ts = pixel clock period 2. for generic tft panel types, the hpp value must be pr ogrammed to 1 and the vpp value must be programmed to 0. this values may be used to configure extended tft types as required. 3. t6typ = t2 - t4 - t5 table 7-48: generic rgb type interface panel horizontal timing symbol parameter min typ max units t1 fpframe falling edge to fpline falling edge hpp (note 2) ts (note 1) t2 horizontal total period ht ts t3 fpline pulse width hpw ts t4 fpline falling edge to drdy active hdps ts t5 horizontal display period hdp ts t6 drdy falling edge to fpline falling edge note 3 ts t7 fpline setup time to fpshift falling edge 0.5 ts t8 drdy setup to fpshift falling edge 0.5 ts t9 fpshift period 1 ts t10 fpshift pulse width high 0.5 ts t11 fpshift pulse width low 0.5 ts t12 drdy hold from fpshift falling edge 0.5 ts t13 data setup to fpshift falling edge 0.5 ts t14 data hold from fpshift falling edge 0.5 ts fpframe fpline drdy fpdat[17:0] t 1 fpshift fpline t2 t3 t4 t5 t6 12 last invalid invalid t7 t8 t9 t10 t11 t12 t13 t14 free datasheet http:///
epson research and development page 91 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential note the generic tft timings are based on the following: fpframe pulse polarity bit is active low (reg[0050h] bit 7 = 0). fpline pulse polarity bit is active low (reg[0046h] bit 7 = 0). generic rgb type interface panel vertical timing figure 7-32: generic rgb type interface panel vertical timing 1. t3 is measured from the first fpline pulse at the start of the frame to the last fpline pulse before fpdat is valid. 2. t3typ = vdps - vpp (for generic tft panel types, the vpp value must be programmed to 0. this value may be used to configure extended tft types as required. table 7-49: generic rgb type interface panel vertical timing symbol parameter min typ max units t1 vertical total period vt line t2 fpframe pulse width vpw line t3 vertical display start position (note 1) note 2 line t4 vertical display period vdp line fpframe drdy fpdat[17:0] t1 fpline t2 t3 t4 line1 invalid invalid last free datasheet http:///
page 92 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.4.2 lcd1 nd-tfd, lcd2 8- bit serial interface timing figure 7-33: lcd1 nd-tfd, lcd2 8-bit serial interface timing fpa0 fpso (msb first) fpcs1# t1 t2 t3 d7 d0 fpso (lsb first) d0 d7 fpcs2# fpsclk (pha = 0, pol = 1) t8 t6 t4 t5 d6 d5 d4 d3 d2 d1 d1 d2 d3 d4 d5 d6 (pha = 0, pol = 0) (pha = 1, pol = 1) (pha = 1, pol = 0) pha: serial clock phase (reg[0054h] bit 1 or reg[005c] bit 1) pol: serial clock polarity (reg[0054h] bit 0 or reg[005c] bit 0) t7 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 fpcs2# fpso t9 t10 lcd2 frame transfer (burst) fpsclk lcd1/lcd2 command/parameter transfer fpa0 t11 t13 t12 free datasheet http:///
epson research and development page 93 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. ts = serial clock period table 7-50: lcd1 nd-tfd, lcd2 8-bit serial interface timing symbol parameter min typ max units t1 chip select setup time 1.5 ts (note 1) t2 data setup time 0.5 ts t3 data hold time 0.5 ts t4 serial clock pulse width low (high) 0.5 ts t5 serial clock pulse width high (low) 0.5 ts t6 serial clock period 1 ts t7 chip select hold time for command/parameter transfer 1.5 ts t8 chip select de-assert to reassert 1 ts t9 chip select setup time at beginning of burst mode 1.5 t10 chip select hold time at end of burst mode 2.5 ts t11 chip select hold time during burst mode 0.5 ts t12 chip select interval in burst mode 1 ts t13 chip select setup time during burst mode 0.5 ts free datasheet http:///
page 94 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.4.3 lcd1 nd-tfd, lcd2 9- bit serial interface timing figure 7-34: lcd1 nd-tfd, lcd2 9-bit serial interface timing fpso (msb first) fpcs1# t1 t2 t3 p/c d1 fpcs2# t8 d7 d6 d5 d4 d3 d2 d0 d7 d6 d5 d4 d3 d2 d1 d0 p/c d7 d6 d5 d4 d3 d2 d1 d0 p/c t9 t12 t11 t13 t7 t10 fpsclk fpso fpcs2# lcd2 frame transfer (burst) lcd1/lcd2 command/parameter transfer fpsclk (pha = 0, pol = 1) t6 t4 t5 (pha = 0, pol = 0) (pha = 1, pol = 1) (pha = 1, pol = 0) fpso (lsb first) p/c d6 d0 d1 d2 d3 d4 d5 d7 pha: serial clock phase (reg[0054h] bit 1 or reg[005c] bit 1) pol: serial clock polarity (reg[0054h] bit 0 or reg[005c] bit 0) free datasheet http:///
epson research and development page 95 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. ts = serial clock period table 7-51: lcd1 nd-tfd, lcd2 9-bit serial interface timing symbol parameter min typ max units t1 chip select setup time 1.5 ts (note 1) t2 data setup time 0.5 ts t3 data hold time 0.5 ts t4 serial clock pulse width low (high) 0.5 ts t5 serial clock pulse width high (low) 0.5 ts t6 serial clock period 1 ts t7 chip select hold time 1.5 ts t8 chip select de-assert to reassert 1 ts t9 chip select setup time at beginning of burst mode 1.5 t10 chip select hold time at end of burst mode 1.5 ts t11 chip select interval in burst mode 1 ts t12 chip select hold time during burst mode 0.5 ts t13 chip select setup time during burst mode 0.5 ts free datasheet http:///
page 96 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.4.4 lcd1 a-si tft serial interface timing figure 7-35: lcd1 a-si tft serial interface timing 1. ts = serial clock period 2. this setting depends on software table 7-52: lcd1 a-si tft serial interface timing symbol parameter min typ max units t1 data setup time 0.5 ts (note 1) t2 data hold time 0.5 ts t3 serial clock plus low period 0.5 ts t4 serial clock pulse high period 0.5 ts t5 serial clock period 1 ts t6 chip select hold time 1.5 ts t7 chip select de-assert to reassert note 2 ts fpso (sdata) fpcs1# (sclk) t1 d0 d6 fpsclk t7 t2 (sstb) t5 t3 t4 d1 d2 d3 d4 d5 d7 invalid t6 free datasheet http:///
epson research and development page 97 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.4.5 lcd1 uwire serial interface timing figure 7-36: lcd1 uwire serial interface timing 1. ts = serial clock period 2. this setting depends on software note when a uwire panel is selected (reg[0054h] bits 7-5 = 10x), fpcs1# idles high until the first uwire transfer is started. after the first transfer, fpcs1# idles low. table 7-53: lcd1 uwire serial interface timing symbol parameter min typ max units t1 chip select setup time 1 ts (note 1) t2 serial clock period 1 ts t3 serial clock pulse width low 0.5 ts t4 serial clock pulse width high 0.5 ts t5 data setup time 0.5 ts t6 data hold time 0.5 ts t7 chip select hold time 1 ts t8 chip select de-assert to reassert note 2 ts (sdi) fpso (lcdcs) fpsclk t1 a7 (sclk) t8 t2 fpcs1# t5 t3 t4 a6 a0 d7 d6 d0 invalid t6 t7 (pha = 1, pol = 0) free datasheet http:///
page 98 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.4.6 lcd1, lcd2 parallel interface timing (80) figure 7-37: lcd1, lcd2 parallel interface timing (80) 1. ts = pixel clock period table 7-54: lcd1, lcd2 parallel interface timing (80) symbol parameter min typ max units t1 chip select falling edge to fpframe (wrx) falling edge 1 ts (note 1) t2 fpframe (wrx) low period 1 ts t3 data setup time for command/parameter transfers 1 ts t4 data hold time 1 ts t5 write signal rising edge to chip select rising edge 1 ts t6 chip select de-assert to reassert 0 ts t7 vertical sync input falling edge to chip select falling edge 51 ts t8 write signal high period in burst cycle 1 ts t9 data setup time for frame transfers 1 ts (a0) fpdat[17:0] (wrx) fpcs1# t1 valid fpframe fpcs2# t6 t2 t3 t5 fpline t1 data1 t2 t9 t5 (a0) fpdat[17:0] (wrx) fpcs1# fpframe fpcs2# fpline lcd1/lcd2 command/parameter transfer lcd1/lcd2 frame transfer (burst) data3 data2 t4 t4 t8 fpvin1 fpvin2 t7 free datasheet http:///
epson research and development page 99 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.4.7 lcd1, lcd2 parallel interface timing (68) figure 7-38: lcd1, lcd2 parallel interface timing (68) 1. ts = pixel clock period table 7-55: lcd1, lcd2 parallel interface timing (68) symbol parameter min typ max units t1 chip select falling edge to fpframe (e) rising edge 1 ts (note 1) t2 fpframe (e) high period 1 ts t3 data setup time for command/parameter transfers 1 ts t4 data hold time 1 t5 fpframe (e) falling edge to chip select rising edge 1 ts t6 chip select deassert to reassert 0 ts t7 vertical sync input falling edge to chip select falling edge 51 ts t8 enable signal low period in burst cycle 1 ts t9 data setup time for frame transfers 1 ts fpline(a0) fpdat[17:0] (e) fpcs1# t1 valid fpframe fpcs2# t6 t2 t3 t5 fpa0 t1 t2 t4 lcd1/lcd2 frame transfer (burst) (a0) fpdat[17:0] (e) fpcs1# fpframe fpcs2# fpline lcd1/lcd2 command/parameter transfer data1 t9 data3 data2 t4 t4 fpvin1 fpvin2 t7 t8 free datasheet http:///
page 100 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.5 output buffer rise/fall time v.s. capacitance (c l ) figure 7-39: rise time v.s. capacitance (c l ) figure 7-40: fall time v.s. capacitance (c l ) table 7-56: rise/fall time v.s. capacitance (c l ) c l (pf) rise time tr (10-90%) [ns] fall time tf (10-90%) [ns] 15 3.413 2.390 50 8.446 5.833 100 15.670 10.840 150 22.910 15.840 200 30.140 20.850 0 10 20 30 40 0 50 100 150 200 hvdd =3. 0v vl=1. 5v ta=25 0 10 20 30 40 0 50 100 150 200 hvdd =3. 0v vl=1. 5v ta=25 free datasheet http:///
epson research and development page 101 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.6 camera interface timing 7.6.1 camera interface timing figure 7-41: camera interface timing 1. ts = system clock period 2. tc = camera block input clock period table 7-57: camera interface timing symbol parameter min max units t1 cmvref rising edge to cmhref rising edge 0 tc (note 1) t2 horizontal blank period 4 tc t3 cmhref falling edge to cmvref falling edge 0 tc t4 vertical blank period 1 line t5 camera input clock period 3 ts (note 2) t6 camera input clock pulse width low 1.5 ts t7 camera input clock pulse width high 1.5 ts t8 data setup time 6 ns t9 data hold time 6 ns t10 cmvref, cmhref setup time 10 ns t11 cmvref, cmhref hold time 10 ns cmdat[7:0] cmvref t5 cmhref t7 t6 t4 line1 line2 last t1 t2 t3 cmclkin t8 t9 t10 t11 cmvref cmhref (vref) (href) (campclk) cmdat[7:0] free datasheet http:///
page 102 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.6.2 camera clock output timing figure 7-42: camera clock output timing 1. system clock = 55mhz, camera clock divide ratio = 2:1 (reg[0100h] bits 4-0 = 00001b) 2. refer to section 7.5, ?output buffer rise/fall time v.s. capacitance (cl)? on page 100 3. t cmduty min = 45% and max. = 55% if the camera clock is less than 13.75mhz (camera clock divide ratio greater than 4:1) table 7-58: camera clock output timing symbol parameter min typ max unit f cmclko camera output clock frequency 27.5 (note 1) mhz t cmclko camera output clock period 1/f cmclko ns t pwh camera output clock pulse width high 6 ns t pwl camera output clock pulse width low 6 ns t r camera output clock rising time (10% - 90%) 8 (note 2) ns t f camera output clock falling time (10% - 90%) 8 (note 2) ns t cmcj camera output clock jitter -2 2 % t cmduty camera output clock duty 40 (note 3) 60 (note 3) % 90% 10% v oh v ol t pwh t pwl t r t f t cmclko t cmcj free datasheet http:///
epson research and development page 103 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.6.3 strobe timing figure 7-43: strobe control output timing 1. this value is determined by reg[1024h] 2. this value is determined by reg[1020h] 3. this value is determined by reg[1022h] table 7-59: strobe control output timing symbol parameter min typ max units t1 cm1vref delay from strobe on - note 1 - t cmv t2 cm1href delay from cmvref active - note 2 - t cmh t3 cmstrout active pulse width - note 3 - t cmh cmstrout t3 t2 cmhref strobe on cmvref cmvref t1 cm 1 vref active select: low (reg[0102h] bit 1 = 0) cm1href active select: low (reg[0102h] bit 2 = 0) cmstrout active select high (reg[0124h] bits 3-0 = 1011b) capture valid camera display control (reg[0930h] bits 1-0 = 00b) free datasheet http:///
page 104 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 7.7 sd memory card interface 7.7.1 sd memory card access figure 7-44: sd memory card access timing table 7-60: sd memory card access timing symbol parameter min max units t1 sdcmd output delay time - 20 ns t2 sdcmd input setup time 10 - ns t3 sdcmd input hold time 5 - ns t4 sddat[3:0] output delay time - 20 ns t5 sddat[3:0] input setup time 10 - ns t6 sddat[3:0] input hold time 5 - ns sdcmd t1 valid (output) sdclk invalid t1 sdcmd (input) t2 t3 sddat[3:0] (output) sddat[3:0] (input) t4 invalid valid invalid invalid t5 t6 free datasheet http:///
epson research and development page 105 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 7.7.2 sd memory card clock output figure 7-45: sd memory card clock output timing table 7-61: sd memory card clock output timing symbol parameter min typ max units f sd sdclk frequency - - 13.75 mhz sd sdclk period - 1/f sd -ns t pwh sdclk width high 10 - - ns t pwl sdclk width low 10 - - ns t r sdclk rising time (10% - 90%) - - 10 ns t f sdclk falling time (10% - 90%) - - 10 ns t sdj sdclk jitter -3 - 3 % t sdd sclk clock duty 40 - 10 % 90% 10% v oh v ol t pwh t pwl t r t f t sd t sdj free datasheet http:///
page 106 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8 memory allocation 8.1 main window case 1 8.1.1 environment ? resolution: 176 x 240 ? color depth: 8 bpp (lut 1)) ? data size: 41.25k bytes ?image: figure 8-1: main window case 1 image display image free datasheet http:///
epson research and development page 107 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? memory map: figure 8-2: memory map for main window case 1 00000h 0a1ffh 07fffh 0ffffh 17fffh 1ffffh 27fffh 2ffffh 37fffh image data 41.25k bytes empty area 182.75k bytes bank1 (128k bytes) bank2 (96k bytes) free datasheet http:///
page 108 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8.2 main window case 2 8.2.1 environment ? resolution: 176 x 240 ? color depth: 16 bpp (lut 1) ? data size: 82.5k bytes ?image: figure 8-3: main window case 2 image display image free datasheet http:///
epson research and development page 109 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? memory map: figure 8-4: memory map for main window case 2 00000h 07fffh 0ffffh 17fffh 1ffffh 27fffh 2ffffh 37fffh 142ffh image data 82.5k bytes empty area 141.5k bytes bank1 (128k bytes) bank2 (96k bytes) free datasheet http:///
page 110 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8.3 main window, pip + window, and overlay display 8.3.1 environment ? resolution: main window image 176 x 240 pip + window image 176 x 220 other panel sizes may be used within the limits of memory capacity. ? color depth: main window image 8 bpp (lut1) pip + window image 16 bpp (lut2) ? data size: main window image 41.25k bytes pip + window image 75.625k bytes ?image: figure 8-5: main window, pip + window, and overlay display overlay main window image pip + window image display image pip + overlay key color free datasheet http:///
epson research and development page 111 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? memory map: figure 8-6: memory map for main window, pip + window, and overlay display image data 54.75k bytes 41.25k bytes empty area 52.375k bytes pip + window area 00000h 07fffh 0ffffh 17fffh 1ffffh 27fffh 2ffffh 37fffh 127ffh bank1 (128k bytes) bank2 (96k bytes) main window area image data 75.625k bytes 295ffh empty area free datasheet http:///
page 112 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8.4 main window, pip + window, overlay, and yuv 8.4.1 environment ? resolution: main window image 176 x 240 pip + window image 176 x 220, from camera interface and resized other panel sizes may be used within the limits of memory capacity. ? color depth: main window image 8 bpp (lut1) pip + window image 16 bpp (lut2) ? data size: main window image 41.25k bytes pip + window image 75.625k bytes ?image: figure 8-7: main window, pip + window, overlay, and yuv overlay key color overlay main window image pip + window image display image pip + from camera interface, resized yuv data to host mail mail free datasheet http:///
epson research and development page 113 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? memory map: figure 8-8: memory map for main window, pip + window, overlay, and yuv image data 54.75k bytes 41.25k bytes empty area 52.375k bytes (pip + window area) 00000h 07fffh 0ffffh 17fffh 1ffffh 27fffh 2ffffh 37fffh 0ccffh bank1 (128k bytes) bank2 (96k bytes) main window area image data 75.625k bytes 295ffh empty area camera image free datasheet http:///
page 114 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8.5 main window, pip + window, overlay, and jpeg 8.5.1 environment ? resolution: main window image 176 x 240 pip + window image 176 x 220 other panel sizes may be used within the limits of memory capacity. ? color depth: main window image 8 bpp (lut1) pip + window image 16 bpp (lut2) ? data size: main window image 41.25k bytes pip + window image 75.625k bytes ?image: figure 8-9: main window, pip + window, overlay, and jpeg overlay jpeg encode to host original data from camera interface main window image display image pip + view resizer pip + window image (176x220) (176x240) overlay key color resizer capture via jpeg fifo free datasheet http:///
epson research and development page 115 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? memory map: figure 8-10: memory map for main window, pip + window, overlay and jpeg line buffer for jpeg operation 32k bytes jpeg fifo for host reading jpeg data 48k bytes (this area is adjustable (this area is reserved automatically) from 4k bytes to 128k bytes) jpeg fifo area image data 41.25k bytes (pip + window area) 00000h 07fffh 0ffffh 17fffh 1ffffh 27fffh 2ffffh 37fffh 0ccffh bank1 (128k bytes) bank2 (96k bytes) main window area image data 75.625k bytes 295ffh camera image 0bbffh jpeg line buffer area free datasheet http:///
page 116 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 9 clocks 9.1 clock diagram figure 9-1: clock diagram pll setting registers pll clki (reg[000eh] bits 15-0, reg[0010h] bits 15-11) pll disable power save mode system clock divide select pixel clock div div system clock serial clock camera clock pixel clock divide select serial clock divide select camera clock divide select div div (reg[0014h] bit 0) (reg[0012h] bit 0) (reg[0030h] bits 10-8) (reg[0100h] bits 3-0) (reg[0030h] bits 4-0) (reg[0018h] bits 1-0) 1 0 div sd card clock divide select (reg[6100h] bits 7-4) sd card clock inclk free datasheet http:///
epson research and development page 117 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 9.2 clocks 9.2.1 system clock system clock (sysclk) is used for the S1D13717 internal main clock. the system clock source can be selected (reg[0012h] bits 2 and 0) from either the internal pll or an external clock input (clki). the system clock divide select bits (reg[0018h] bits 1-0) control this clock division. the system clock can be a divided down version of the output of the pll or the input of clki. 9.2.2 pixel clock pixel clock (pclk) is used for the lcd1 shift clock of a rgb type panel and for the lcd1/lcd2 parallel interface timing. the pixel clock source is always the system clock and can be divided using the pixel clock divide select bits (reg[0030h] bits 4-0). 9.2.3 serial clock serial clock (sclk) is used for the lcd1 and lcd2 serial interfaces. the serial clock source is always the system clock and can be divided using the serial clock divide select bits (reg[0030h] bits 10-8). 9.2.4 camera clock camera clock (camclk) is used for the camera interface. the camera clock source is always the system clock and can be divided using the camera clock divide select bits (reg[0100h] bits 3-0). note this clock can be output on cmclkout to be used as the master clock of an external camera module attached to the camera interface. 9.2.5 sd memory card clock the sd memory card clock is output to the external sd memory card as the sd card clock. the sd memory card clock source is always the system clock and can be divided using the sd memory card clock divide select bits (reg[6100h] bits 7-4). free datasheet http:///
page 118 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10 registers 10.1 register mapping the S1D13717 registers are memory-mapped. when the system decodes the input pins as cs# = 0 and m/r# = 0 (for 1 cs# mode), or cs# = 1 and m/r# = 0 (for 2 cs# mode), the registers may be accessed. the register space is decoded by ab[17:1] and be#[1:0], and is mapped as follows. table 10-1: S1D13717 register mapping m/r# address function 1 00000h to 37fffh sram memory 0 0000h to 0007h system configuration registers 0 000eh to 0019h clock setting registers 0 0020h to 002bh indirect interface registers 0 0030h to 003dh lcd panel interface setting registers 0 0040h to 0057h lcd1 setting registers 0 0058h to 005fh lcd2 setting registers 0 0100h to 0125h camera interface registers 0 0200h to 024fh display mode setting registers 0 0300h to 030dh gpio registers 0 0310h to 0329h overlay registers 0 0400h to 08ffh look-up table registers 0 0930h to 096fh resizer operation registers 0 0980h to 098bh jpeg module registers 0 09a0h to 09bch jpeg fifo setting registers 0 09c0h to 09e1h jpeg line buffer setting registers 0 0a00h to 0a41h interrupt control registers 0 0f00h to 0f01h jpeg encode performance register 0 1000h to 17a3h jpeg codec registers 0 6000h to 613fh sd memory card interface registers 0 8000h to 8033h 2d bitblt registers 0 10000h 2d accelerator data port free datasheet http:///
epson research and development page 119 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.2 register set the s1d13719 registers are listed in the following table. table 10-2: S1D13717 register set register pg register pg system configuration registers reg[0000h] product information register 124 reg[0002h] configuration pins status register 124 reg[0006h] bus timeout setting register 125 clock setting registers reg[000eh] pll setting register 0 126 reg[0010h] pll setting register 1 128 reg[0012h] pll setting register 2 128 reg[0014h] miscellaneous configuration register 129 reg[0016h] software reset register 131 reg[0018h] system clock setting register 131 indirect interface registers reg[0020h] is reserved 132 reg[0022h] indirect interface memory address register 1 132 reg[0024h] indirect interface memory address register 2 132 reg[0026h] indirect interface auto increment register 133 reg[0028h] indirect interface memory access port register 133 reg[002ah] indirect interface 2d bitblt data read/write port register 133 lcd panel interface generic setting registers reg[0030h] lcd interface clock setting register 134 reg[0032h] lcd module clock setting register 136 reg[0034h] lcd interface command register 137 reg[0036h] lcd interface parameter register 138 reg[0038h] lcd interface status register 138 reg[003ah] lcd interface frame transfer register 139 reg[003ch] lcd interface transfer setting register 139 lcd1 setting register reg[0040h] lcd1 horizontal total register 141 reg[0042h] lcd1 horizontal display period register 141 reg[0044h] lcd1 horizontal display period start position register 142 reg[0046h] lcd1 fpline register 142 reg[0048h] lcd1 fpline pulse position register 142 reg[004ah] lcd1 vertical total register 143 reg[004ch] lcd1 vertical display period register 143 reg[004eh] lcd1 vertical display period start position register 143 reg[0050h] lcd1 fpframe register 144 reg[0052h] lcd1 fpframe pulse position register 144 reg[0054h] lcd1 serial interface setting register 145 reg[0056h] lcd1 parallel interface setting register 146 lcd2 setting registers reg[0058h] lcd2 horizontal display period register 148 reg[005ah] lcd2 vertical display period register 148 reg[005ch] lcd2 serial interface setting register 148 reg[005eh] lcd2 parallel interface setting register 149 reg[0070h] through reg[00feh] are reserved 150 camera interface setting register reg[0100h] camera clock setting register 151 reg[0102h] camera signal setting register 151 reg[0104h] through reg[010eh] are reserved 152 re g[0110h] camera mode setting register 153 reg[0112h] camera frame setting register 155 reg[0114h] camera control register 156 reg[0116h] camera status register 157 reg[0120h] strobe line delay register 159 reg[0122h] strobe pulse width register 159 reg[0124h] strobe control register 160 reg[0128h] through reg[012fh] are reserved 161 free datasheet http:///
page 120 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential display mode setting register reg[0200h] display mode setting register 0 162 re g[0202h] display mode setting register 1 164 reg[0204h] transparent overlay key color red data register 167 reg[0206h] transparent overlay key color green data register 167 reg[0208h] transparent overlay key color blue data register 168 reg[0210h] main window display st art address register 0 168 reg[0212h] main window display start addres s register 1 168 reg[0214h] main window start address status register 169 reg[0216h] main window line address offset register 170 re g[0218h] pip+ display start address register 0 171 reg[021ah] pip+ display start address register 1 171 reg[ 021ch] pip+ window start address status register 172 reg[021eh] pip+ window line address offset register 173 reg[0220h] pip+ x start positions register 174 reg[0222h] pip+ y start positions register 174 reg[0224h] pip+ x end positions register 175 reg[0226h] pip+ y end positions register 175 reg[0228h] is reserved 175 reg[022ah] back buffer display start address register 0 176 reg[ 022ch] back buffer display start address register 1 176 reg[0240h] yuv/rgb translate mode register 176 reg[0242h] yuv/rgb converter write start address 0 register 0 180 reg[0244h] yuv/rgb converter write start address 0 register 1 180 reg[0246h] yuv/rgb converter write start address 1 register 0 180 reg[0248h] yuv/rgb converter write start address 1 register 1 180 reg[024ah] uv data fix register 181 reg[024ch] yrc rectangle pixel width register 181 reg[024e h] yrc rectangular line address offset register 181 reg[0268h] is reserved 181 reg[0280h] is reserved 181 gpio registers reg[0300h] gpio status and control register 0 182 reg[0304h] gpio status and control register 3 182 reg[0308h] gpio pull down control register 0 183 reg[030ch] gpio status and control register 4 183 overlay registers reg[0310h] average overlay key color red data register 184 reg[0312h] average overlay key color green data register 184 reg[0314h] average overlay key color blue data register 185 reg[0316h] and overlay key color red data register 185 reg[0318h] and overlay key color green data register 186 reg[031ah] and overlay key color blue data register 186 reg[031ch] or overlay key color red data register 187 reg[031eh] or overlay key color green data register 187 reg[0320h] or overlay key color blue data register 188 reg[0322h] inv overlay key color red data register 188 reg[0324h] inv overlay key color green data register 189 reg[0326h] inv overlay key color blue data register 189 reg[0328h] overlay miscellaneous register 190 lut1 (main window) registers reg[0400 - 07fch] lut1 data register 0 192 reg[0402 - 07feh] lut1 data register 1 192 lut2 (pip+ window) registers reg[0800 - 08fch] lut2 data register 0 193 reg[0802 - 08feh] lut2 data register 1 193 resizer operation registers reg[0930h] global resizer control register 194 reg[0932h] through reg[093eh] are reserved 196 reg[0940h] view resizer control register 197 reg[09 44h] view resizer start x position register 198 reg[0946h] view resizer start y position register 198 reg[0948h] view resizer end x position register 199 reg[094ah] view resizer end y position register 199 reg[09 4ch] view resizer operation setting register 0 199 reg[094eh] view resizer operation setting register 1 202 reg[0960h] capture resizer control register 202 reg[0964h] capture resizer start x position register 203 reg[0966h] capture resizer start y position register 204 reg[0968h] capture resizer end x position register 204 re g[096ah] capture resizer end y position register 204 reg[096ch] capture resizer operation setting register 0 205 re g[096eh] capture resizer operation setting register 1 208 table 10-2: S1D13717 register set register pg register pg free datasheet http:///
epson research and development page 121 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential jpeg module registers reg[0980h] jpeg control register 209 reg[0982h] jpeg status flag register 214 reg[0984h] jpeg raw status flag register 218 reg[0986h] jpeg interrupt control register 221 reg[0988h] is reserved 222 reg[098ah] jpeg code start/stop control register 223 reg[098ch] through reg[098eh] are reserved 223 jpeg fifo setting register reg[09a0h] jpeg fifo control register 224 reg[09a2h] jpeg fifo status register 225 reg[09a4h] jpeg fifo size register 226 reg[09a6h] jpeg fifo read/write port register 227 reg[09a8h] jpeg fifo valid data size register 227 reg[09aah] jpeg fifo read pointer register 227 reg[09ach] jpeg fifo write pointer register 228 reg[09b0h] encode size limit register 0 228 reg[09b2h] encode size limit register 1 228 reg[09b4h] encode size result register 0 229 reg[09b6h] encode size result register 1 229 reg[09b8h] jpeg file size register 0 229 reg[09bah] jpeg file size register 1 229 reg[09bch] is reserved 229 jpeg line buffer setting register reg[09c0h] jpeg line buffer status flag register 230 reg[ 09c2h] jpeg line buffer raw status flag register 231 reg[09c4h] jpeg line buffer raw current status register 232 reg[09c6h] jpeg line buffer interrupt control register 232 reg[09c8h] through reg[09ceh] are reserved 233 reg[09d0h] jpeg line buffer configuration register 233 reg[09d2h] jpeg line buffer address offset register 233 reg[09d4h] through reg[09deh] are reserved 234 reg[09e0h] jpeg line buffer read/write port register 234 interrupt control registers reg[0a00h] interrupt status register 235 re g[0a02h] interrupt control register 0 236 reg[0a04h] interrupt control register 1 236 reg[0a06h] debug status register 237 reg[0a08h] interrupt control for debug register 238 reg[ 0a0ah] host cycle interrupt status register 239 reg[0a0ch] host cycle interrupt control register 240 reg[0a0eh] cycle time out control register 241 reg[0a10h] is reserved 242 reg[0a40h] interrupt request status register 242 jpeg encode performance register reg[0f00h] jpeg encode performance register 243 jpeg codec registers reg[1000h] operation mode setting register 244 reg[1002h] command setting register 245 reg[1004h] jpeg operation status register 246 reg[1006h] quantization table number register 246 reg[1008h] huffman table number register 247 reg[100ah] dri setting register 0 248 reg[100ch] dri setting register 1 248 reg[100eh] vertical pixel size register 0 249 reg[1010h] vertical pixel size register 1 249 reg[1012h] horizontal pixel size register 0 250 reg[1014h] horizontal pixel size register 1 250 reg[1016h] dnl value setting register 0 251 reg[1018h] dnl value setting register 1 251 reg[101ah] is reserved 251 reg[101ch] rst marker operation setting register 252 re g[101eh] rst marker operation status register 253 reg[1020 - 1066h] insertion marker data register 254 reg[1200 - 127eh] quantization table no. 0 register 254 reg[1280 - 12feh] quantization table no. 1 register 254 reg[1400 - 141eh] dc huffman table no. 0 register 0 255 reg[1420 - 1436h] dc huffman table no. 0 register 1 255 reg[1440 - 145eh] ac huffman table no. 0 register 0 256 reg[1460 - 15a2h] ac huffman table no. 0 register 1 256 reg[1600 - 161eh] dc huffman table no. 1 register 0 258 reg[1620 - 1636h] dc huffman table no. 1 register 1 258 reg[1640 - 165eh] ac huffman table no. 1 register 0 259 reg[1660 - 17a2h] ac huffman table no. 1 register 1 259 table 10-2: S1D13717 register set register pg register pg free datasheet http:///
page 122 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential sd memory card interface registers reg[6000h] sd memory card configuration register 0 261 reg[6002h] sd memory card configuration register 1 262 reg[6004h] sd memory card configuration register 2 264 reg[6100h] sd memory card control register 0 266 reg[6102h] sd memory card control register 1 267 reg[6104h] sd memory card function register 268 reg[6106h] sd memory card status register 270 reg[6108h] sd memory card data length register 0 272 reg[610ah] sd memory card data length register 1 272 reg[610ch] sd memory card command register 272 reg[610eh] sd memory card timer register 272 reg[6110h] sd memory card parameter register 0 273 reg[6112h] sd memory card parameter register 1 273 re g[6114h] sd memory card parameter register 2 273 reg[6116h] sd memory card parameter register 3 273 reg[6118h~611eh] sd memory card data register 274 reg[6120h] sd memory card response register 0 274 re g[6122h] sd memory card response register 1 274 reg[6124h] sd memory card response register 2 275 re g[6126h] sd memory card response register 3 275 reg[6128h] sd memory card response register 4 275 re g[612ah] sd memory card response register 5 275 reg[612ch] sd memory card response register 6 276 re g[612eh] sd memory card response register 7 276 reg[6130h] sd memory card response register 8 276 re g[6132h] sd memory card response register 9 276 reg[6134h] sd memory card response register a 277 re g[6136h] sd memory card response register b 277 reg[6138h] sd memory card response register c 277 re g[613ah] sd memory card response register d 277 reg[613ch] sd memory card response register e 278 re g[613eh] sd memory card response register f 278 2d bitblt registers reg[8000h] bitblt control register 0 279 reg[8002h] bitblt control register 1 279 reg[8004h] bitblt status register 0 280 reg[8006h] is reserved 280 reg[8008h] bitblt command register 0 281 reg[800ah] bitblt command register 1 282 reg[800ch] bitblt source start address register 0 283 re g[800eh] bitblt source start address register 1 283 reg[8010h] bitblt destination start address register 0 284 re g[8012h] bitblt destination start address register 1 284 reg[8014h] bitblt memory address offset register 284 reg[8018h] bitblt width register 284 reg[801ch] bitblt height register 285 reg[8020h] bitblt background color register 285 reg[8024h] bitblt foreground color register 285 reg[8030h] bitblt interrupt status register 285 reg[8032h] bitblt interrupt control register 286 reg[10000h] 2d bitblt data memory mapped region register 286 table 10-2: S1D13717 register set register pg register pg free datasheet http:///
epson research and development page 123 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.3 register restrictions all reserved bits must be set to 0 unless otherwise specified. writing a value to a reserved bit may produce undefined results. bits marked as n/a have no hardware effect. some registers are only accessible when certain conditions exist. any attempts to read/write in-accessible registers are invalid. the following restrictions apply to all registers. ? reg[0000h] - reg[0018h] and reg[0300h] - reg[030ch] are always accessible. ? reg[0000h] - reg[0018h] are not reset by a software reset. ? when power save mode is enabled (reg[0014h] bit 0 = 1), reg[0030h] - reg[0f00h] are not accessible. ? when the jpeg codec is disabled (reg[0980h] bit 0 = 0), reg[1000h] - reg[17a2h] are not accessible. ? when the sd card interface is disabled (reg[6000h] bit 0 = 0), reg[6100h] - reg[613eh] are not accessible. free datasheet http:///
page 124 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4 register description 10.4.1 system configuration registers bits 15-8 display buffer size bits [7:0] (read only) these bits indicate the size of the sram display buffer measured in 4k byte increments. the S1D13717 display buffer is 224k bytes and these bits return a value of 56 (38h). reg[0000h] bits 15-8 = display buffer size 4k bytes = 224k bytes 4k bytes = 56 (38h) bits 7-2 product code bits [5:0] (read only) these bits indicate the product code. the product code for the S1D13717 is 011001b (19h). bits 1-0 revision code bits [1:0] (read only) these bits indicate the revision code. the revision code is 00b. bits 6-0 cnf[6:0] status (read only) these status bits return the status of the configuration pins cnf[6:0]. cnf[6:0] are latched at the rising edge of reset#. for a functional description of each configuration bit (cnf[6:0]), see section 5.3, ?summary of configuration options? on page 42. reg[0000h] product information register default = 3864h read only display buffer size bits 7-0 15 14 13 12 11 10 9 8 product code bits 5-0 revision code bits 1-0 76543210 reg[0002h] configuration pins status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a cnf[6:0] status 76543210 free datasheet http:///
epson research and development page 125 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 2 bus timeout reset interrupt status (read only). this is the status bit for the bus timeout reset function. bus timeout reset occurs when the wait# signal is active for 2 or 3 cycles. this is the status bit for the bus timeout function. when this bit = 1, a bus timeout has occurred. when this bit = 0, a bus timeout has not occurred. this flag is cleared by the bus timeout reset interrupt disable bit (reg[0006h] bit 0). bit 1 bus timeout reset disable this bit controls the bus timeout reset function of the S1D13717. if a bus timeout occurs, the bus timeout reset interrupt status is set (reg[0006h] bit 2) and the chip is reset. when this bit = 0, the bus timeout reset function is enabled (default). when this bit = 1, the bus timeout reset function is disabled. note when the internal pll is disabled (reg[0012h] bit 0 = 1), the bus timeout function must be disabled (reg[0006h] bit 1 = 1). bit 0 bus timeout reset interrupt disable this bit controls the bus timeout reset interrupt and is used to clear the bus timeout reset interrupt status (reg[0006h] bit 2). when this bit = 0, the bus timeout interrupt is enabled (default). when this bit = 1, the bus timeout interrupt is disabled. when this bit is written as 1, the bus timeout flag (reg[0006h] bit 2) is cleared. reg[0006h] bus timeout setting register default = 0000h read/write n/a 15 14 13 13 11 10 9 8 n/a bus timeout reset interrupt status (ro) bus timeout reset disable bus timeout reset interrupt disable 7 6 5 4 3210 free datasheet http:///
page 126 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.2 clock setting registers note before setting this register, power save mode must be enabled (reg[0014h] bit 0 = 1) and the pll must be disabled (reg[0012h] bit 0 = 1). for more information, see figure 11-1: ?power-on/power-off sequence,? on page 287 or figure 11-2: ?power modes,? on page 288. bits 15-12 n-counter bits [3:0] bits 11-2 l-counter bits [9:0] these bits are used together to configure the pll output (in mhz) and must be set according to the following formula. pll output = (n-counter +1) x (l-counter +1) x clki = nn x ll x clki where: pll output is the desired pll output frequency in mhz (55mhz max) n-counter is the value in bits 15-12 l-counter is the value in bits 11-2 clki is the pll reference frequency (should always be 32.768khz) note to optimize power consumption, use the largest nn value possible. reg[000eh] pll setting register 0 default = 1be8h read/write n-counter bits 3-0 l-counter bits 9-6 15 14 13 12 11 10 9 8 l-counter bits 5-0 v-divider bits 1-0 76543210 table 10-3: pll setting example target freq. (mhz) nn ll nn x ll reg[000eh] pout (mhz) 40 4 305 1220 34c0h 39.98 45 6 229 1374 5390h 45.02 48.76 16 93 1488 f194h 48.76 50 15 122 1830 e1e4h 49.97 54 16 103 1648 f198h 54.00 55 2 839 1678 1d18h 54.98 free datasheet http:///
epson research and development page 127 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 1-0 v-divider bits [1:0] these bits are used to fine tune the pll output jitter. the v-divider bits represent a value as shown in the following table. the v-divider bits must be set such that the following formula is valid. 100mhz pll output x v-divider 410mhz where: pll output in mhz (55mhz max) generated by bits 15-12 (n-counter) and bits 11-2 (l-counter) v-divide is the value from table 10-4: note setting the v-divider value to 00 provides the lowest possible power consumption, but the most jitter. specific system design requirements should be considered to achieve the optimal setting. table 10-4: v-divider reg[000eh] bits 1-0 v-divider 00 see note 01 2 10 4 11 8 free datasheet http:///
page 128 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential note before setting this register, power save mode must be enabled (reg[0014h] bit 0 = 1) and the pll must be disabled (reg[0012h] bit 0 = 1). for more information, see figure 11-1: ?power-on/power-off sequence,? on page 287 or figure 11-2: ?power modes,? on page 288. bits 15-12 vco kv set bits [3:0] these bits are used to fine tune the pll output jitter. these bits should be set as follows. if 100mhz (pll output x v-divider) 200mhz, set these bits to 0010. if 200mhz < (pll output x v-divider) 300mhz, set these bits to 0101. if 300mhz < (pll output x v-divider) 410mhz, set these bits to 0111. all other non-zero values for these bits are reserved. where: pll output is the desired pll output frequency in mhz and is generated using reg[000eh] bits 15-12 and reg[000eh] bits 11-2 v-divide is the value from table 10-4: and is controlled by reg[000eh] bits 1-0 note setting the value of these bits to 0000 provides the lowest possible power consumption, but the most jitter. specific system design requirements should be considered to achieve the optimal setting. note for more information on the pll and clock structure, see section 9, ?clocks? on page 116. bit 2 reserved the default value for this bit is 0. bit 1 reserved the default value for this bit is 0. reg[0010h] pll setting register 1 default = 0000h read/write vco kv set bits 3-0 n/a 15 14 13 12 11 10 9 8 n/a 7 6 5 4 3 2 1 0 reg[0012h] pll setting register 2 default = 0001h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved reserved pll disable 7 6 5 4 3210 free datasheet http:///
epson research and development page 129 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 pll disable this bit controls the internal pll. the pll must be configured using pll setting regis- ter 0 (reg[000eh]) and pll setting register 1 (reg[0010h]) before enabling this bit. when this bit = 0, the pll is enabled. when this option is selected, the pll output is the source for the system clock divider. when this bit = 1, the pll is disabled (default). when this option is selected, the external clock, clki is the source for the system clock divider. note there may be up to a 100ms delay before the pll output becomes stable. the S1D13717 must not be accessed during this time. bit 12 reserved the default value for this bit is 0. bit 11 reserved the default value for this bit is 0. bit 10 reserved the default value for this bit is 0. bit 9 lcd2 serial bypass mode select this bit selects bypass mode for the lcd2 display. this bit must be configured before the serial/parallel port bypass enable bit (reg[0032h] bit 8) is set. if reg[0032h] bit 8 is set to 1 when this bits = 0, there is no hardware effect. for bypass mode pin mapping, see table 5-14: ?serial bypass pin mapping,? on page 47. when this bit = 0, serial bypass of lcd2 is not possible. when this bit = 1, serial bypass of lcd2 is possible when mode 1 (reg[0032h] bits 1-0 = 00b) or mode 2 (reg[0032h] bits 1-0 = 10b) is selected. bit 8 reserved the default value for this bit is 0. bit 7 vertical non-display period status (read only) if an rgb type panel is selected for lcd1 (mode 1/mode 4, see reg[0032h] bits 1-0), this status bit indicates whether the panel is in a vertical non-display period. this bit has no effect when mode 2 or mode 3 is selected. when this bit = 0, the lcd panel output is in a vertical display period. when this bit = 1, the lcd panel output is in a vertical non-display period. reg[0014h] miscellaneous configuration register default = 0011h read/write n/a reserved reserved reserved lcd2 serial bypass mode select reserved 15 14 13 12 11 10 9 8 vndp status (ro) memory controller idle status (ro) n/a serial/parallel input active pull-up/pull-down enable n/a reserved reserved power save enable 76 54 3210 free datasheet http:///
page 130 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 6 memory controller idle status (read only) this bit indicates the status of the memory controller and must be checked before enabling power save mode (reg[0014h] bit 0) or disabling the pll (reg[0012h] bit 0). for fur- ther information on using this bit, see figure 11-1: ?power-on/power-off sequence,? on page 287 or figure 11-2: ?power modes,? on page 288. when this bit = 0, the memory controller is powered up. when this bit = 1, the memory controller is idling and the system clock source can be dis- abled. bit 4 serial input active pull-up/pull-down enable this bit controls the active pull-up/pull-down resistors on the host serial input pins (scs#, sclk, sa0, si). when the serial input port is unused (hi-z), set this bit to 1. when this bit = 0, the pull-up/pull-down resistors are inactive. when this bit = 1, the pull-up/pull-down resistors are active and the pins are affected as follows (default). bit 2 reserved the default value for this bit is 0. bit 1 reserved the default value for this bit is 0. bit 0 power save mode enable this bit controls the state of the software initiated power save mode. when power save mode is disabled, the S1D13717 is operating normally. when power save mode is enabled, the S1D13717 is in a power efficient state. for more information on the S1D13717 condition during power save mode, see section 11.2, ?power save mode function? on page 290. when this bit = 0, power save mode is disabled. when this bit = 1, power save mode is enabled (default). note for all modes except mode 1 (see reg[0032h] bits 1-0), the lcd output port must be turned off (reg[0202h] bits 12-10 = 000b) before enabling power save mode. for all modes, the memory controller idle status bit (reg[0014h] bit 6) must return a 1 before enabling power save mode. table 10-5: serial pull-up/pull-down resistors pin type scs# pull-up sclk pull-down sa0 pull-down si pull-down free datasheet http:///
epson research and development page 131 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 15-0 software reset bits [15:0] (write only) when any value is written to these bits, all registers are reset to their default values . a software reset via this register does not clear the display buffer . for further information on software reset, see section 11.1.2, ?reset? on page 289. bits 1-0 system clock divide select bits [1:0] these bits determine the divide ratio for the system clock. the source is selectable, using reg[0012h] bit 0, between either the pll output (see reg[000eh]-reg[0012h]) or an external clock source (clki). note for more information on clocks, see section 9, ?clocks? on page 116. reg[0016h] software reset register default = not applicable write only software reset bits 15-8 15 14 13 12 11 10 9 8 software reset bits 7-0 76543210 reg[0018h] system clock setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a system clock divide select bits 1-0 7 6 5 4 3 210 table 10-6: system clock divide ratio selection reg[0018h] bits 1-0 system clock divide ratio 00b 1:1 01b 2:1 10b 3:1 11b 4:1 free datasheet http:///
page 132 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.3 indirect interface registers these registers are used for the indirect interface only. the indirect interface is selected at reset# using the configuration bits cnf[4:2] (see table 5-10: ?summary of power- on/reset options,? on page 42). for examples using the indirect interface, see section 22, ?indirect interface? on page 372. reg[0020h] is reserved this register is reserved and should not be written. reg[0024h] bits 2-0 reg[0022h] bits 15-1 indirect interface memory address bits [18:1] this register is used for indirect interface modes only. these bits determine the memory start address for each memory access. after a completed memory access, this register is incremented automatically. note only 16-bit memory accesses are possible when an indirect interface is selected. reg[0022h] indirect interface memory address register 1 default = 0000h read/write indirect interface memory address bits 15-8 15 14 13 12 11 10 9 8 indirect interface memory address bits 7-1 n/a 7654321 0 reg[0024h] indirect interface memory address register 2 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a indirect interface memory address bits 18-16 7 6 5 4 3210 free datasheet http:///
epson research and development page 133 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 1-0 indirect interface auto increment bits [1:0] this register is used for indirect interface modes only. these bits determine the method used to auto increment the memory address stored in the indirect interface memory address registers (reg[0024h]-[0022h]). the indirect inter- face memory address registers must be auto incremented after each memory access based on the type of memory accesses being done (byte or word). bits 15-0 indirect interface memory access port bits [15:0] this register is used for indirect interface modes only. these bits are the memory read/write port for the indirect interface. an index write to this register begins (or triggers) a burst read/write to memory. bits 15-0 indirect interface 2d bitblt data read/write port bits [15:0] this register is used for indirect interface modes only. these bits are the read/write port for 2d bitblt data when using the indirect interface (instead of reg[10000h] for direct addressing). reg[0026h] indirect interface auto increment register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a indirect interface auto increment bits 1-0 7 6 5 4 3 210 table 10-7: indirect interface auto increment selection reg[0026h] bits 1-0 indirect interface auto increment 00b (default) increment when a high byte access or word access takes place 01b increment only when a word access takes place (no increment takes place for byte accesses) 10b never increment (auto increment is disabled) 11b reserved reg[0028h] indirect interface memory access port register default = not applicable read/write indirect interface memory access port bits 15-8 15 14 13 12 11 10 9 8 indirect interface memory access port bits 7-0 76543210 reg[002ah] indirect interface 2d bitblt data read/write port register default = not applicable read/write indirect interface 2d bitblt data read/write port bits 15-8 15 14 13 12 11 10 9 8 indirect interface 2d bitblt data read/write port bits 7-0 76543210 free datasheet http:///
page 134 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.4 lcd panel interface generic setting registers bits 10-8 serial clock divide select bits[2:0] these bits specify the divide ratio for the serial clock. the clock source for the serial clock is the system clock (see figure 9-1: ?clock diagram,? on page 116). if lcd1 or lcd2 is not a serial interface type lcd panel (reg[0032h] bits 1-0) or if serial port bypass is enabled (reg[0032h] bit 8 = 1), these bits are ignored. reg[0030h] lcd interface clock setting register default = 0000h read/write n/a serial clock divide select bits 2-0 15 14 13 12 11 10 9 8 n/a pixel clock divide select bits 4-0 7 6 543210 table 10-8: serial clock divide ratio selection reg[0030h] bits 10-8 serial clock divide ratio 000b 2:1 001b 4:1 010b 6:1 011b 8:1 100b 10:1 101b 12:1 110b 14:1 111b 16:1 free datasheet http:///
epson research and development page 135 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 4-0 pixel clock divide select bits[4:0] these bits specify the divide ratio for the pixel clock. the clock source for the pixel clock is the system clock (see figure 9-1: ?clock diagram,? on page 116). when lcd1 is an rgb type panel (reg[0032h] bits 1-0 = 00b or 01b), the pixel clock is the same as the shift clock. when lcd1 or lcd2 is a parallel interface type panel (reg[0032h] bits 1-0 = 10b or 11b), the pixel clock is used for the parallel data output timing clock. note swivelview should not be used when the 2:1 pixel clock divide ratio is used (reg[0202h] bits 5-4 = 00b and bits 1-0 = 00b). table 10-9: pixel clock divide selection reg[0030h] bits 4-0 pixel clock divide ratio 00000b 2:1 00001b 4:1 00010b 6:1 00011b 8:1 00100b 10:1 00101b 12:1 00110b 14:1 00111b 16:1 01000b 18:1 01001b 20:1 01010b 22:1 01011b 24:1 01100b 26:1 01101b 28:1 01110b 30:1 01111b 32:1 10000b 34:1 10001b 36:1 10010b 38:1 10011b 40:1 10100b 42:1 10101b 44:1 10110b 46:1 10111b 48:1 11000b - 11111b reserved free datasheet http:///
page 136 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 15-10 reserved the default value for these bits is 0. bit 8 serial port bypass enable this bit controls the serial port bypass function. to enable the serial port bypass, set reg[0014h] bit 9 = 1, then reg[0032h] bit 8 =1. when the serial port bypass is enabled, the host can drive the lcd2 serial interface directly via the host serial interface. when the serial port bypass is disabled, the lcd2 serial interface is controlled by the S1D13717. for serial bypass pin mapping and input/output port assignments, see table 5-14: ?serial bypass pin mapping,? on page 47. when this bit = 0, the serial port bypass is disabled. when this bit = 1, the serial port bypass is enabled. note the lcd output port select bits (reg[0202h] bits 12-10) and panel interface bits (reg[0032h] bits 1-0) have no effect in serial bypass mode. note when power save mode is enabled (reg[0014h] bit 0 = 1), the host can drive the lcd2 serial interface directly via the host serial interface automatically. in this situation, the serial port bypass enable bit does not need to be set. bit 7 fpshift polarity select this bit sets the polarity of the shift clock for rgb type panels (inverts fpshift). when this bit = 0, all panel interface signals change at the rising edge of fpshift. when this bit = 1, all panel interface signals change at the falling edge of fpshift. bits 6-4 rgb interface panel data bus width bits [2:0] these bits only have an effect when a rgb interface panel is selected (reg[0032h] bits 1-0 = 00b or 01b). these bits determine the rgb interface panel data bus size. unused fpdat[17:0] pins are forced low. reg[0032h] lcd module clock setting register default = 0000h read/write reserved n/a serial port bypass enable 15 14 13 12 11 10 98 fpshift polarity select rgb interface panel data bus width bits 2-0 n/a panel interface bits 1-0 7654 3 210 table 10-10: rgb interface panel data bus width selection reg[0032h] bits 6-4 rgb interface panel data bus width (lcd1) 000b 9-bit 001b 12-bit 010b 16-bit 011b 18-bit 100b - 111b reserved free datasheet http:///
epson research and development page 137 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 1-0 panel interface bits[1:0] these bits determine the lcd1 and lcd2 interface types. bit 15-0 lcd interface command register bits [15:0] these bits are only for parallel/serial interface panels on lcd1 or lcd2 and have no effect for rgb type panels. these bits form the command register for the lcd1/lcd2 parallel/serial interfaces. for 8-bit parallel or serial interfaces, only the lower byte is used. when the lcd interface is busy (reg[0038h] bit 0 = 1), this register must not be written. when the lcd interface is not busy (reg[0038h] bit 0 = 0), the command transfer starts when this register is written. when the command transfer starts, the fpa0 pin is driven low or high depending on the state of the p/c polarity invert enable bit (reg[003ch] bit 7). note if the lcd1 serial data type is set to uwire (reg[0054h] bits 7-5 = 10xb), the upper byte of reg[0034h] is used for a[7:0] and the lower byte is used for d[7:0]. table 10-11: panel interface selection reg[0032h] bits 1-0 mode lcd1 panel interface lcd2 panel interface 00b 1 rgb interface serial interface (ram integrated) 01b 4 rgb interface parallel interface (ram integrated) 10b 2 parallel interface (ram integrated) serial interface (ram integrated) 11b 3 parallel interface (ram integrated) parallel interface (ram integrated) reg[0034h] lcd interface command register default = 0000h read/write lcd interface command register bits 15-8 15 14 13 12 11 10 9 8 lcd interface command register bits 7-0 76543210 free datasheet http:///
page 138 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 15-0 lcd interface parameter register bits [15:0] these bits are only for parallel/serial interface panels on lcd1 or lcd2 and have no effect for rgb type panels. these bits form the parameter register for the lcd1/lcd2 parallel/serial interfaces. for 8-bit parallel or serial interfaces, only the lower byte is used. when the lcd interface is busy (reg[0038h] bit 0 = 1), this register must not be written. when the lcd interface is not busy (reg[0038h] bit 0 = 0), data transfer starts when this register is written. when the data transfer starts, the fpa0 pin is driven high or low depending on the state of the p/c polarity invert enable bit (reg[003ch] bit 7). note if the lcd1 serial data type is set to uwire (reg[0054h] bits 7-5 = 10xb), the upper byte of reg[0036h] is used for a[7:0] and the lower byte is used for d[7:0]. bit 0 lcd interface status (read only) this bit indicates the status of the lcd1 or lcd2 serial/parallel interface. when this bit = 0, the lcd1 or lcd2 serial/parallel interface is not busy (or ready). when this bit = 1, the lcd1 or lcd2 serial/parallel interface is busy. reg[0036h] lcd interface parameter register default = 0000h read/write lcd interface parameter register bits 15-8 15 14 13 12 11 10 9 8 lcd interface parameter register bits 7-0 76543210 reg[0038h] lcd interface status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a lcd interface status 7 6 5 4 3 2 10 free datasheet http:///
epson research and development page 139 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 lcd interface frame transfer trigger this bit is only for parallel/serial interface panels on lcd1 or lcd2 and has no effect for rgb type panels. this bit is the trigger to transfer 1 frame of data to the lcd interface. when this bit is set to 1 and the lcd interface status is not busy (reg[0038h] bit 0 = 0), 1 frame of data is transferred to the lcd interface. when the data transfer is finished, this bit is cleared automatically. when this bit is set to 1 and the lcd interface is busy (reg[0038h] bit 0 = 1), the frame transfer request is ignored. once the lcd interface is no longer busy, this bit is cleared without transferring any data. note when lcd interface auto transfer is enabled (reg[003ch] bit 0 = 1), this bit remains high (1). bit 7 parameter/command polarity invert enable this bit is only for parallel/serial interface panels on lcd1 or lcd2 and has no effect for rgb type panels. during an lcd interface command (reg[0034h]) or lcd interface parameter (reg[0036h]) transfer, fpa0 is driven high or low based on the set- ting of this bit. when lcd1 is a nd-tfd 9-bit panel (reg[0054h] bits 7-5 = 001) or lcd2 is a 9-bit serial panel (reg[005ch] bit 5 = 1), this bit determines the msb of the 9- bit data on fpso. reg[003ah] lcd interface frame transfer register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a lcd interface frame transfer trigger 7 6 5 4 3 2 10 reg[003ch] lcd interface transfer setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 p/c polarity invert enable n/a lcd interface auto frame transfer enable 7 6 5 4 3 2 10 table 10-12: parameter/command invert setting reg[003ch] bit 7 fpa0 signal output command parameter 0 low high 1highlow free datasheet http:///
page 140 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 lcd interface auto frame transfer enable this bit is only for parallel/serial interface panels on lcd1 or lcd2 and has no effect for rgb type panels. this bit controls the automatic frame transfer of one frame of display memory to the lcd interface. the frame transfer is triggered and synchronized by the camera interface vertical sync signal (cmvref). all camera input signals are required to trigger the frame transfer. when this bit = 0, auto frame transfer is disabled. when this bit = 1, auto frame transfer is enabled. when this bit = 1, the lcd interface status bit (reg[0038h] bit 0) is always busy. when busy, command/parameter and frame transfers cannot be sent manually. this bit should be disabled before camera input is disabled. note while auto transfer is enabled, the following condition must be met or no frame trans- fers will take place. 1 frame transfer cycle (time) < 1 cmvref period (time) note while auto transfer is enabled, do not vary the pclk and cm1clkout/cm2clkout frequencies free datasheet http:///
epson research and development page 141 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.5 lcd1 setting register bits 9-7 reserved the default value for these bits is 0. bits 6-0 lcd1 horizontal total bits [6:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the lcd1 horizontal total period, in 8 pixel resolution. the horizontal total is the sum of the horizontal display period and the horizontal non-display period. the maximum horizontal total is 1024 pixels. these bits must not be set to 0. reg[0040h] bits 6-0 = (horizontal total in pixels 8) - 1 note this register must be programmed such that the following formula is valid. ht hdp + hndp bits 8-0 lcd1 horizontal display period bits [8:0] these bits specify the lcd1 horizontal display period, in 2 pixel resolution. the hori- zontal display period must be less than the horizontal total to allow for a sufficient hori- zontal non-display period. reg[0042h] bits 8-0 = (horizontal display period in pixels 2) - 1 note for parallel interface panels (see reg[0032h] bits 1-0), the following formula must be valid. hdp x vdp 40 pixels. reg[0040h] lcd1 horizontal total register default = 0001h read/write n/a reserved 15 14 13 12 11 10 9 8 reserved lcd1 horizontal total bits 6-0 76543210 reg[0042h] lcd1 horizontal display period register default = 0000h read/write n/a lcd1 hdp bit 8 15 14 13 12 11 10 98 lcd1 horizontal display period bits 7-0 76543210 free datasheet http:///
page 142 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 9-0 lcd1 horizontal display period start position bits [9:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the lcd1 horizontal display period start position in 1 pixel resolution. reg[0044h] bits 9-0 = horizontal display period start position in pixels - 9 bit 7 fpline pulse polarity this bit is for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and has no effect when a serial or parallel interface panel is selected. this bit selects the polar- ity of the horizontal sync signal (fpline). when this bit = 0, the horizontal sync signal (fpline) is active low. when this bit = 1, the horizontal sync signal (fpline) is active high. bits 6-0 fpline pulse width bits [6:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the width of the horizontal sync signal (fpline), in 1 pixel resolution. reg[0046h] bits 6-0 = fpline pulse width in pixels - 1 bits 9-0 fpline pulse position bits [9:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the position of the fpline pulse. reg[0048h] bits 9-0 = fpframe edge to fpline edge in pixels - 1 reg[0044h] lcd1 horizontal display period start position register default = 0000h read/write n/a lcd1 hdp bits 9-8 15 14 13 12 11 10 9 8 lcd1 horizontal display period bits 7-0 76543210 reg[0046h] lcd1 fpline register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 fpline polarity fpline pulse width bits 6-0 76543210 reg[0048h] lcd1 fpline pulse position register default = 0000h read/write n/a fpline pulse position bits 9-8 15 14 13 12 11 10 9 8 fpline pulse position bits 7-0 76543210 free datasheet http:///
epson research and development page 143 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 9-0 lcd1 vertical total bits [9:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the lcd1 vertical total period, in 1 line resolution. the vertical total is the sum of the vertical display period and the vertical non-display period. the maximum vertical total is 1024 lines. reg[004ah] bits 9-0 = vertical total in lines - 1 bits 9-0 lcd1 vertical display period bits [9:0] these bits specify the lcd1 vertical display period, in 1 line resolution. the vertical display period must be less than the vertical total to allow for a sufficient vertical non- display period. reg[004ch] bits 9-0 = vertical display period in lines - 1 note for parallel interface panels (see reg[0032h] bits 1-0), the following formula must be valid. hdp x vdp 40 pixels bits 9-0 lcd1 vertical display period start position bits [9:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the lcd1 vertical display period start position in 1 line resolution. reg[004ah] lcd1 vertical total register default = 0000h read/write n/a lcd1 vertical total bits 9-8 15 14 13 12 11 10 9 8 lcd1 vertical total bits 7-0 76543210 reg[004ch] lcd1 vertical display period register default = 0000h read/write n/a lcd1 vertical display period bits 9-8 15 14 13 12 11 10 9 8 lcd1 vertical display period bits 7-0 76543210 reg[004eh] lcd1 vertical display period start position register default = 0000h read/write n/a lcd1 vertical display period start position bits 9-8 15 14 13 12 11 10 9 8 lcd1 vertical display period start position bits 7-0 76543210 free datasheet http:///
page 144 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 7 lcd1 fpframe pulse polarity this bit is for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and has no effect when a serial or parallel interface panel is selected. this bit selects the polar- ity of the vertical sync signal (fpframe). when this bit = 0, the vertical sync signal (fpframe) is active low. when this bit = 1, the vertical sync signal (fpframe) is active high. bits 2-0 lcd1 fpframe pulse width bits [2:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the width of the panel vertical sync signal (fpframe), in 1 line resolution. reg[0050h] bits 2-0 = fpframe pulse width in lines - 1 bits 9-0 lcd1 fpframe pulse position bits [9:0] these bits are for rgb interface panels only (reg[0032h] bits 1-0 = 00b or 01b) and have no effect when a serial or parallel interface panel is selected. these bits specify the start position of the fpframe signal, in 1 line resolution. reg[0050h] lcd1 fpframe register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 fpframe polarity n/a lcd1 fpframe pulse width bits 2-0 7 6 5 4 3210 reg[0052h] lcd1 fpframe pulse position register default = 0000h read/write n/a lcd1 fpframe pulse position bits 9- 8 15 14 13 12 11 10 9 8 lcd1 fpframe pulse position bits 7-0 76543210 free datasheet http:///
epson research and development page 145 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 7-5 lcd1 serial data type bits [2:0] these bits determine the lcd1 serial data type for rgb displays requiring initialization through a serial interface. note for mode 2 and mode 3 configurations (see reg[0032h] bits 1-0), these bits must be set to 000b. bit 4 lcd1 serial data direction this bit determines the lcd1 serial data direction for rgb displays requiring initializa- tion through a serial interface. when this bit = 0, the msb is first. when this bit = 1, the lsb is first. bit 1 lcd1 serial clock phase this bit specifies the serial clock phase for rgb displays requiring initialization through a serial interface. see table 10-14: ?lcd1 serial clock polarity and phase selection?. note for details on timing, see section 7.4.2, ?lcd1 nd-tfd, lcd2 8-bit serial interface timing? on page 92. reg[0054h] lcd1 serial interface setting register default = 0001h read/write n/a 15 14 13 12 11 10 9 8 lcd1 serial data type bits 2-0 lcd1 serial data direction n/a lcd1 serial clock phase lcd1 serial clock polarity 7654 3 210 table 10-13: lcd1 serial data type selection reg[0054h] bits 7-5 lcd1 serial data type 000b nd-tfd 4 pins (8-bit serial) 001b nd-tfd 3 pins (9-bit serial) 01xb a-si tft (8-bit serial) 10xb uwire (16-bit serial) 11xb reserved free datasheet http:///
page 146 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 lcd1 serial clock polarity this bit determines the lcd1 serial data format for rgb displays requiring initialization through a serial interface. note for details on timing, see section 7.4.2, ?lcd1 nd-tfd, lcd2 8-bit serial interface timing? on page 92. bit 13 reserved the default value for this bit is 0. bit 12 reserved the default value for this bit is 0. bits 9-8 reserved these bits are reserved and default to 0. bit 7 lcd1 vsync input enable this bit is not used for rgb type panels. this bit allows the transfer of a frame of data synced to an external vsync input (fpvin1). when a manual transfer has been initiated, the lcd1 data output will occur on the next falling edge of fpvin1. when this bit = 0, the lcd1 data output is independent of an external vsync input. when this bit = 1, the lcd1 data output is synchronous with an external vsync input. note the fpvin1 signal period must be longer than the time it takes to transfer a frame of data. if the fpvin1 period is shorter than the time it takes to transfer a complete frame to the panel, the current frame transfer is interrupted at the next fpvin1 falling edge. note once a manual frame transfer has been initiated (reg[003ah] bit 0 = 1), the lcd1 vsync input enable bit must not be disabled before the next vsync signal has oc- curred or the lcd interface will always be busy and subsequent transfers will not occur. table 10-14: lcd1 serial clock polarity and phase selection reg[0054h] bit 1 reg[0054h] bit 0 serial data output changes idling status of clock 0 0 falling edge of serial clock low 1 rising edge of serial clock high 1 0 rising edge of serial clock low 1 falling edge of serial clock high reg[0056h] lcd1 parallel interface setting register default = 0000h read/write n/a reserved reserved n/a reserved 15 14 13 12 11 10 9 8 lcd1 vsync input enable lcd1 parallel type select n/a lcd1 parallel data format bits 2-0 76 5 4 3210 free datasheet http:///
epson research and development page 147 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 6 lcd1 parallel type select this bit determines the lcd1 parallel interface type. when this bit = 0, the parallel interface is type 80. when this bit = 1, the parallel interface is type 68. bit 2-0 lcd1 parallel data format bits [2:0] these bits determine the lcd1 parallel data format. these bits are not used for rgb type panels (reg[0032h] bits 1-0 = 00 or 01) . for further information on available par- allel data formats, see section 13.4, ?parallel data format? on page 299. table 10-15: lcd1 parallel data format selection reg[0056h] bits 2-0 lcd1 parallel data format data bus width data format 000b 8-bit rgb = 3:3:2 (1 cycle/pixel) 001b rgb = 4:4:4 (3 cycle / 2 pixel) 010b 16-bit rgb = 8:8:8 (3 cycle/2 pixel) 011b 8-bit rgb = 8:8:8 (3 cycle/pixel) 100b reserved 101b 16-bit rgb = 4:4:4 (1 cycle/pixel) 110b rgb = 5:6:5 (1 cycle/pixel) 111b 18-bit rgb = 6:6:6 (1 cycle/pixel) free datasheet http:///
page 148 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.6 lcd2 setting registers bits 8-0 lcd2 horizontal display period bits [8:0] these bits specify the lcd2 horizontal display period, in 2 pixel resolution. reg[0058h] bits 8-0 = (horizontal display period in pixels 2) - 1 note for parallel and serial interface panels (see reg[0032h] bits 1-0), the following formu- la must be valid. hdp x vdp 40 pixels. bits 9-0 lcd2 vertical display period bits [9:0] these bits specify the lcd2 vertical display period, in 1 line resolution. reg[005ah] bits 9-0 = vertical display period in lines - 1 note for parallel and serial interface panels (see reg[0032h] bits 1-0), the following formu- la must be valid. hdp x vdp 40 pixels. bit 5 lcd2 serial data type this bit determines the lcd2 serial data type. reg[0058h] lcd2 horizontal display period register default = 0000h read/write n/a lcd2 hdp bit 8 15 14 13 12 11 10 98 lcd2 horizontal display period bits 7-0 76543210 reg[005ah] lcd2 vertical display period register default = 0000h read/write n/a lcd2 vertical display period bits 9-8 15 14 13 12 11 10 9 8 lcd2 vertical display period bits 7-0 76543210 reg[005ch] lcd2 serial interface setting register default = 0001h read/write n/a 15 14 13 12 11 10 9 8 n/a lcd2 serial data type lcd2 serial data direction lcd2 serial data format bits 1-0 lcd2 serial clock phase lcd2 serial clock polarity 7 6543210 table 10-16: lcd2 serial data type selection reg[005ch] bit 5 lcd2 serial data type 0 4 pins (8-bit) 1 3 pins (9-bit) free datasheet http:///
epson research and development page 149 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 4 lcd2 serial data direction this bit determines the lcd2 serial data direction. when this bit = 0, the msb is first. when this bit = 1, the lsb is first. bit 3-2 lcd2 serial data format bits[1:0] these bits determine the lcd2 serial data format. for further information on available serial data formats, see section 13.5, ?serial data format? on page 305. bit 1 lcd2 serial clock phase this bit specifies the lcd2 serial clock phase. see table 10-18: ?lcd2 serial clock polarity and phase selection?. note for details on timing, see section 7.4.2, ?lcd1 nd-tfd, lcd2 8-bit serial interface timing? on page 92. bit 0 lcd2 serial clock polarity this bit determines the lcd2 serial clock polarity. note for details on timing, see section 7.4.2, ?lcd1 nd-tfd, lcd2 8-bit serial interface timing? on page 92. bit 13 reserved the default value for this bit is 0. table 10-17: lcd2 serial data format selection reg[005ch] bits 3-2 lcd2 serial data format data length data format 00b 8-bit rgb=3.3.2 (1 transfer / pixel) 01b rgb=4.4.4 (3 transfer / 2 pixel) 10b reserved 11b table 10-18: lcd2 serial clock polarity and phase selection reg[005ch] bit 1 reg[005ch] bit 0 serial data output changes clock idling status 0 0 falling edge of serial clock low 1 rising edge of serial clock high 1 0 rising edge of serial clock low 1 falling edge of serial clock high reg[005eh] lcd2 parallel interface setting register default = 0000h read/write n/a reserved reserved n/a 15 14 13 12 11 10 9 8 lcd2 vsync input enable lcd2 parallel type select n/a lcd2 parallel data format bits 2-0 76 5 4 3210 free datasheet http:///
page 150 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 12 reserved the default value for this bit is 0. bit 7 lcd2 vsync input enable this bit allows the transfer of a frame of data synced to an external vsync input (fpvin2). when a manual transfer has been initiated, the lcd1 data output will occur on the next falling edge of fpvin1. when this bit = 0, the lcd2 data output is independent of an external vsync input. when this bit = 1, the lcd2 data output is synchronous with an external vsync input. note the fpvin2 signal period must be longer than the time it takes to transfer a frame of data. if the fpvin2 period is shorter than the time it takes to transfer a complete frame to the panel, the current frame transfer is interrupted at the next fpvin2 falling edge. bit 6 lcd2 parallel type select this bit determines the lcd2 parallel interface type. when this bit = 0, the parallel interface is type 80. when this bit = 1, the parallel interface is type 68. bits 2-0 lcd2 parallel data format bits[2:0] these bits determine the lcd2 parallel data format. for further information on available parallel data formats, see section 13.4, ?parallel data format? on page 299. reg[0070h] through reg[00feh] are reserved these registers are reserved and should not be written. table 10-19: lcd2 parallel data format selection reg[005eh] bits 2-0 lcd2 parallel data format data bus width data format 000b 8-bit rgb=3.3.2 (1 cycle/pixel) 001b rgb=4.4.4 (3 cycle / 2 pixel) 011b rgb=8.8.8 (3 cycle/pixel) 101b 16-bit rgb=4.4.4 (1 cycle/pixel) 110b rgb=5.6.5 (1 cycle/pixel) 111b 18-bit rgb=6.6.6 (1 cycle/pixel) 010b 16-bit rgb=8.8.8 (3 cycle/2 pixel) 100b reserved free datasheet http:///
epson research and development page 151 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.7 camera interface setting register bits 4-0 camera clock divide select bits [4:0] these bits specify the divide ratio used to generate the camera clock from the system clock. bit 6 reserved the default value for this bit is 0. bit 5 camera clock mode select this bit determines the source of the clock used to sample incoming yuv data on the camera interface. when this bit = 0, the external input clock (cmclkin) from the camera interface is used to sample incoming yuv data (default). when this bit = 1, the internally divided system clock is used to sample incoming yuv data. reg[0100h] camera clock setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a camera clock divide select bits 4-0 7 6 543210 table 10-20: camera clock divide ratio selection reg[0100h] bits 4-0 camera clock divide ratio reg[0100h] bits 4-0 camera clock divide ratio 00000b 1:1 10000b 17:1 00001b 2:1 10001b 18:1 00010b 3:1 10010b 19:1 00011b 4:1 10011b 20:1 00100b 5:1 10100b 21:1 00101b 6:1 10101b 22:1 00110b 7:1 10110b 23:1 00111b 8:1 10111b 24:1 01000b 9:1 11000b 25:1 01001b 10:1 11001b 26:1 01010b 11:1 11010b 27:1 01011b 12:1 11011b 28:1 01100b 13:1 11100b 29:1 01101b 14:1 11101b 30:1 01110b 15:1 11110b 31:1 01111b 16:1 11111b 32:1 reg[0102h] camera signal setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved camera clock mode select camera yuv data format select bits 1-0 camera hsync active select camera vsync active select camera valid input clock edge 76543210 free datasheet http:///
page 152 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 4-3 camera yuv data format select bits [1:0] these bits specify the yuv data format for the camera interface, in bytes. bit 2 camera hsync active select this bit defines hysnc for the camera interface. when this bit = 0, the camera hsync (cmhref) is active low and cmhref high means data is valid. when this bit = 1, the camera hsync (cmhref) is active high and cmhref low means data is valid. bit 1 camera vsync active select this bit defines vysnc for the camera interface. when this bit = 0, the camera vsync (cmvref) is active low and cmvref high means data is valid. when this bit = 1, the camera vsync (cmvref) is active high and cmvref low means data is valid. bit 0 camera valid input clock edge this bit determines the edge on which camera data is latched. when this bit = 0, the S1D13717 latches input data on the rising edge of the clock (cmclkin). when this bit = 1, S1D13717 latches input data on the falling edge of the clock (cmclkin). reg[0104h] through reg[010eh] are reserved these registers are reserved and should not be written. table 10-21: yuv data format selection reg[0102h] bits 4-3 yuv data format (8-bit format) 00b (1st) uyvy (last) 01b (1st) vyuy (last) 10b (1st) yuyv (last) 11b (1st) yvyu (last) free datasheet http:///
epson research and development page 153 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 15 reserved the default value for this bit is 0.bit 13reserved the default value for this bit is 0. bit 12 camera active pull-down disable this bit controls the active pull-down resistors on the camera interface. when this bit = 0, the active pull-down resistors on the camera interface are enabled. when this bit = 1, the active pull-down resistors on the camera interface are disabled. bit 10 camera clock sampling mode this bit controls the camera clock sampling rate. when this bit = 0, the sampling rate is ?normal mode?. when this bit = 1, the sampling rate is ?fast mode?. when fast mode is selected the camera clock di vide select bits must be set to 1:1 or 1:2 (reg[0100h] bits 4-0 = 0000b or 0001b). bit 9 reserved the default value for this bit is 0. reg[0110h] camera mode setting register default = 0000h read/write reserved n/a reserved camera active pull-down disable n/a camera clock sampling mode reserved yuv data offset enable 15 14 13 12 11 10 9 8 itu-r bt656 enable reserved cmclkout output disable reserved camera module enable 76543 2 10 free datasheet http:///
page 154 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 8 yuv data offset enable this bit determines whether the incoming u and v data from the camera interface is inter- nally offset. typically, camera modules output in yuv or ycbcr offset format, therefore this bit is cleared or set to 0. if the camera data is intended for viewing after the yuv/rgb converter (yrc), or encoding through the jpeg codec, the resulting yuv data format should be yuv or ycbcr offset. when this bit = 0, no offset is applied to the incoming u and v camera (uv values are unmodified). when this bit = 1, an offset is applied to the incoming u and v camera data, the incoming u and v camera data msb are inverted. note for yuv to rgb converter (yrc) input requirements, see the bit description for reg[0240h] bit 4. bit 7 itu-r bt656 enable this bit controls the active camera interface type and is valid when the interface type is yuv 4:2:2 8-bit (see reg[0102h] bit 6). when this bit = 0, the normal camera interface is active. in this mode the hsync, vsync, clock, and data signals are independent. when this bit = 1, the itu-r bt656 camera interface is active. in this mode the hsync and vsync signals are mixed with the data signals. bits 6-4 reserved the default value for these bits is 0. bit 3 cmclkout output disable this bit controls (enables/disables) the camera clock output (cmclkout). when this bit = 0, the camera clock output is enabled (default). when this bit = 1, the camera clock output is disabled (low output). table 10-22: yuv/yuv offset enable reg[0110h] bits 8 yuv data offset input data range output data range 0 no offset is applied 0 y 255 same as input -128 u 127 -128 v 127 16 y 235 -113 u 112 -113 v 112 1 camera format: yuv straight range converted to yuv offset range 0 y 255 0 y 255 0 u 255 -128 u 127 0 v 255 -128 v 127 camera format: ycbcr straight range converted to ycbcr offset range 16 y 235 16 y 235 16 u 240 -113 u 112 16 v 240 -113 v 112 free datasheet http:///
epson research and development page 155 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 2-1 reserved the default value for these bits is 0. bit 0 camera module enable this bit controls the camera module. when this bit = 0, the camera module and clock output (cmclkout) are disabled. when this bit = 1, the camera module and clock output (cmclkout) are enabled. bit 7 camera frame capture interrupt control this bit controls when the camera frame capture interrupt is asserted and depends on the setting of the camera single frame capture mode bit (reg[0112h] bit 6) as follows. for continuous frame capture mode (reg[0112h] bit 6 = 0): when this bit = 0, the interrupt is generated when a valid frame is captured. this result also depends on the camera frame capture interrupt status always active bit (reg[0112h] bit 5). when this bit = 1, the interrupt is generated after a valid frame is captured and the capture is stopped. for single frame capture mode (reg[0112h] bit 6 = 1): when this bit = 0, the interrupt is generated when a valid frame is captured. this result also depends on the camera frame capture interrupt status always active bit (reg[0112h] bit 5). when this bit = 1, the interrupt is generated when a valid frame is captured. note when this bit = 1, the camera frame capture interrupt status always active bit (reg[0112h] bit 5) has no effect on camera frame interrupt generation. bit 6 camera single frame capture enable this bit controls the camera frame capture mode of the camera interface. this bit must not be changed while the camera module is enabled (reg[0110h] bit 0 = 1). when this bit = 0, frames from the camera interface are continuously captured. when this bit = 1, the next frame from the camera interface is captured when a camera frame capture start command is issued (reg[0114h] bit 2 = 1). the camera frame capture stops after a single frame is captured. reg[0112h] camera frame setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 camera frame capture interrupt control camera single frame capture enable camera frame capture interrupt status always active frame sampling control bits 2-0 camera frame capture interrupt polarity camera frame capture interrupt enable 76543210 free datasheet http:///
page 156 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 5 camera frame capture interrupt status always active when camera frame capture interrupts are enabled (reg[0112h] bit 0 =1b) this bit enables triggering of the camera frame capture interrupt on all captured camera frames. this bit has no effect if camera frame capture interrupts are disabled when this bit = 0, the camera frame capture interrupt flag is only active when the jpeg start/stop control bit is on, reg[098ah] bit 0 =1. when this bit = 1, the camera frame capture interrupt flag is active on all captured camera frames. bits 4-2 frame sampling control bits [2:0] these bits control the camera data sampling rate in frames. bit 1 camera frame capture interrupt trigger polarity this bit controls the assertion timing of the camera frame capture interrupt. when this bit = 0, the camera frame capture interrupt is asserted when vsync is active. when this bit = 1, the camera frame capture interrupt is asserted when vsync is inac- tive. bit 0 camera frame capture interrupt enable this bit controls whether a camera frame capture interrupt is generated or not. when this bit = 0, the camera frame capture interrupt is disabled. when this bit = 1, the camera frame capture interrupt is enabled. bit 9 itu-r bt656 error flag 1 clear (write only) this bit only has an effect when itu-r bt656 interface mode is active (reg[0110h] bit 7 = 1). writing a 0 to this bit has no hardware effect. writing a 1 to this bit clears the itu-r bt656 error flag 1 (reg[0116h] bit 9). table 10-23: frame sampling control selection reg[0112h] bits 4-2 frame sampling mode 000b every frame is sampled 001b 1 frame is sampled for every 2 frames 010b 1 frame is sampled for every 3 frames 011b 1 frame is sampled for every 4 frames 100b 1 frame is sampled for every 5 frames 101b 1 frame is sampled for every 6 frames 110b 1 frame is sampled for every 7 frames 111b reserved reg[0114h] camera control register default = 0000h write only n/a itu-r bt656 error flag 1 clear itu-r bt656 error flag 0 clear 15 14 13 12 11 10 9 8 n/a camera frame capture stop camera frame capture start camera frame cap[ture interrupt status clear camera module software reset 7 6 5 43210 free datasheet http:///
epson research and development page 157 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 8 itu-r bt656 error flag 0 clear (write only) this bit only has an effect when itu-r bt656 interface mode is active (reg[0110h] bit 7 = 1). writing a 0 to this bit has no hardware effect. writing a 1 to this bit clears the itu-r bt656 error flag 0 (reg[0116h] bit 8). bit 3 camera frame capture stop (write only) this bit stops image frame capturing from the camera interface. writing a 0 to this bit has no hardware effect. writing a 1 to this bit stops image frame capturing. bit 2 camera frame capture start (write only) this bit starts image frame capturing from the camera interface. writing a 0 to this bit has no hardware effect. writing a 1 to this bit starts image frame capturing. bit 1 camera frame capture interrupt status clear (write only) this bit clears the camera frame capture interrupt status bit (reg[0116h] bit 1). writing a 0 to this bit has no hardware effect. writing a 1 to this bit clears the camera frame capture interrupt status. bit 0 camera module software reset (write only) this bit initializes the camera module logic. camera interface registers are not affected. writing a 0 to this bit has no hardware effect. writing a 1 to this bit initializes the camera module. bit 9 itu-r bt656 error flag 1 (read only) this bit only has an effect when itu-r bt656 interface mode is active (reg[0110h] bit 7 = 1). when this bit = 0, no error has occurred. when this bit = 1, a 2-bit error is detected on the reference decode operation. to clear this bit, see reg[0114h] bit 9. bit 8 itu-r bt656 error flag 0 (read only) this bit only has an effect when itu-r bt656 interface mode is active (reg[0110h] bit 7 = 1). when this bit = 0, no error has occurred. when this bit = 1, a 1-bit error is detected on the reference decode operation. to clear this bit, see reg[0114h] bit 8. reg[0116h] camera status register default = 0044h read only n/a itu-r bt656 error flag 1 itu-r bt656 error flag 0 15 14 13 12 11 10 9 8 n/a camera vsync effective strobe frame status effective frame status camera frame capture busy status camera frame capture start/stop flag camera frame capture interrupt status n/a 7654321 0 free datasheet http:///
page 158 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 6 camera vsync (read only) this bit indicates the current condition of vsync from the camera interface. when this bit = 0, vsync is not currently occurring. when this bit = 1, vsync is currently occurring. bit 5 effective strobe frame status (read only) this bit indicates the status of the valid data captured when the strobe is enabled (reg[0124h] bit 0 = 1). this bit goes high when the valid frame for the strobe pulse is captured. it will only remain high for one frame and then go low. this bit returns a 0, when there is no valid data. this bit returns a 1, when the valid frame for the strobe pulse is captured. it remains high for only one frame and then goes low. bit 4 effective frame status (read only) this bit indicates whether the current frame from the camera interface is an ?effective? frame based on the frame sampling control bits (reg[0112h] bit 4-2). when this bit = 0, an effective frame is not occurring. when this bit = 1, an effective frame is occurring. the following diagram shows an example of the effective frame status bit where the frame sampling control bits are set for 1 frame sampled for every 3 frames (reg[0112h] bits 4-2 = 010b). figure 10-1: effective frame status bit example bit 3 camera frame capture busy status (read only) this bit indicates the status of frame capturing from the camera interface. when this bit = 0, frames are not being captured. when this bit = 1, frames are being captured. bit 2 camera frame capture start/stop flag (read only) this bit indicates the current state of the camera frame capture setting in relation to the setting of the camera frame capture start/stop bits (reg0114h] bits 3-2). when this bit = 0, camera frame capturing has been stopped. when this bit = 1, the camera frame capturing start command has been asserted. camera vsync valid valid invalid invalid invalid reg[0116h] bit 5 camera data effective frame status reg[0116h] bit 4 free datasheet http:///
epson research and development page 159 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 1 camera frame capture interrupt status (read only) this bit indicates when a camera frame capture interrupt has taken place. this bit is masked by the camera frame capture interrupt enable bit (reg[0112h] bit 0) and cleared using the camera frame capture interrupt status clear bit (reg[0114h] bit 1). when this bit = 0, a camera frame capture interrupt has not occurred. when this bit = 1, a camera frame capture interrupt has occurred. note when the camera frame capture interrupt is enabled (reg[0112h] bit 0 = 1) and the camera frame capture interrupt status always active is enabled (reg[0112h] bit 5 = 0), the camera frame capture interrupt is only set at the first camera vref if continuous capture mode is selected (reg[0112h] bit 6 = 0). note this bit is set regardless of whether the resizers are enabled. therefore, the camera frame capture interrupt status bit cannot be used as an indication that a camera frame has been written to the embedded memory or the jpeg codec. bit 15-0 strobe line delay bits [15:0] when the strobe is enabled (reg[0124h] bit 0 = 1), these bits specify the delay, in lines of the camera interface, from the first hsync input of a camera frame to the beginning of the strobe control signal. for details on the strobe control signal, see section 20.2, ?strobe control signal? on page 367. bit 15-0 strobe pulse width bits [15:0] when the strobe is enabled (reg[0124h] bit 0 = 1), these bits specify the pulse width of the strobe control signal, in lines of the camera interface. for details on the strobe con- trol signal, see section 20.2, ?strobe control signal? on page 367. reg[0120h] strobe line delay register default = 0000h read/write strobe line delay bits 15-8 15 14 13 12 11 10 9 8 strobe line delay bits 7-0 76543210 reg[0122h] strobe pulse width register default = 0000h read/write strobe pulse width bits 15-8 15 14 13 12 11 10 9 8 strobe pulse width bits 7-0 76543210 free datasheet http:///
page 160 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 7-4 strobe capture delay control bits [3:0] when the strobe is enabled (reg[0124h] bit 0 = 1) and continuous frame capture mode is enabled (reg[0112h] bit 6 = 0), these bits specify the delay, in camera frames, of the cap- tured camera data. bit 3 strobe enable this bit enables the strobe control signal (cmstrout). when this bit = 0, the strobe is disabled and cmstrout is high (default). when this bit = 1, the strobe is enabled and cmstrout is actively driven (high/low). bit 2 strobe port data this bit determines the output of cmstrout and only has an effect when the output mode of the strobe port is configured for general purpose output (reg[0124h] bit 0 = 0) and the strobe is enabled (reg[0124h] bit 3 = 1). when this bit = 0, the output is low (default). when this bit = 1, the output is high. bit 1 strobe control signal polarity this bit selects output polarity of the strobe control signal. when this bit = 0, the strobe control signal is active low. when this bit = 1, the strobe control signal is active high. reg[0124h] strobe control register default = 0009h read/write n/a 15 14 13 12 11 10 9 8 strobe capture delay control bits 3-0 strobe enable strobe port data strobe control signal polarity strobe port select 76543210 table 10-24: strobe capture delay control reg[0124h] bits 7-4 delay value 0000b no delay 0001b 1 frame 0010b 2 frames 0011b 3 frames 0100b 4 frames 0101b 5 frames 0110b 6 frames 0111b 7 frames 1000b 8 frames 1001b 9 frames 1010b 10 frames 1011b 11 frames 1100b 12 frames 1101b 13 frames 1110b 14 frames 1111b 15 frames free datasheet http:///
epson research and development page 161 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 strobe port select this bit configures the output mode of the strobe port (cmstrout). when this bit = 0, the strobe port is a general purpose output port (default). in this mode cmstrout can be used for general purpose data output. when this bit = 1, the strobe port is configured for the strobe (or flash) function. for fur- ther information on this function, see section 20.2, ?strobe control signal? on page 367. in this mode cmstrout outputs a strobe pulse triggered by: ? the jpeg start/stop control bit (reg[098ah] bit 0 = 1) ? the frame capture stop bit for repeat capture mode (reg[0114h] bit 2 = 1) ? the frame capture start bit for single frame capture mode (reg[0114h] bit 3 = 1) reg[0128h] through reg[012fh] are reserved these registers are reserved and should not be written. free datasheet http:///
page 162 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.8 display mode setting register bit 13 double buffer window select this bit controls which window (main or pip + ) is affected when double buffer mode is enabled (reg[0200h] bit 12 = 1). when this bit = 0, the pip + window area is double buffered. when this bit = 1, the main window area is double buffered. bit 12 double buffer mode enable this bit controls double buffer mode. when double buffer mode is enabled, the window to be double buffered must be selected using the double buffer window select bit (reg[0200h] bit 13). the corresponding main/pip + window area settings, such as the display start address and the line address offset registers, specify the front buffer dis- play start address and line address offset. the back buffer uses the same line address offset as the front buffer, however it?s display start address is now controlled by the back buffer display start address registers (reg[022ch]-[022ah]). the following table summarizes the possible address and offset configurations. when this bit = 0, double buffer mode is disabled. when this bit = 1, double buffer mode is enabled. double buffer mode in combination with double buffer write mode (reg[0240h] bit 5 = 1) can be used to enhance the performance of the camera interface, allowing the display to be refreshed from one buffer while the camera interface is writing data to the other buffer. note if double buffer mode is enabled, but single buffer write mode is selected (reg[0240h] bit 5 = 0), only the back buffer image is displayed on the selected window (see reg[0200h] bit 13). bit 10 reserved the default value for this bit is 0. reg[0200h] display mode setting register 0 default = 0000h read/write n/a double buffer window select double buffer mode enable n/a reserved display mode select bits 1-0 15 14 13 12 11 10 9 8 lcd software reset (wo) reserved lut2 bypass enable lut1 bypass enable pip+ window bpp select bits 1-0 main window bpp select bits 1-0 76543210 table 10-25: double buffer address registers double buffer window select (reg[0200h] bit 13) front buffer back buffer start address offset start address offset double buffer = main reg[0212h]-[0210h] reg[0216h] reg[022ch]-[022ah] reg[0216h] double buffer = pip + reg[021ah]-[0218h] reg[021eh] reg[022ch]-[022ah] reg[021eh] free datasheet http:///
epson research and development page 163 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 9-8 display mode select bits[1:0] these bits determine the display mode for either lcd1 or lcd2 depending on the setting of the lcd output port select bits (reg[0202h] bits 12-10). bit 7 lcd software reset (write only) when this bit is set to 0, there is no hardware effect. when this bit is set to 1, a software reset is performed on the lcd interface. bit 6 reserved the default value for this bit is 0. bit 5 lut2 bypass enable lut2 is associated with the pip + window. this bit determines if lut2 is used for output to the pip + window. for more information on the display format when lut2 is used or bypassed, see section 13, ?display data formats? on page 295. when this bit = 0, lut2 is used. when this bit = 1, lut2 is bypassed. bit 4 lut1 bypass enable lut1 is associated with the main window. this bit determines if lut1 is used for output to the main window. for more information on the display format when lut1 is used or bypassed, see section 13, ?display data formats? on page 295. when this bit = 0, lut1 is used. when this bit = 1, lut1 is bypassed. bit 3-2 pip + window bits-per-pixel select bits[1:0] these bits determine the color depth for the pip + window. for more information, see sec- tion 13, ?display data formats? on page 295. table 10-26: display mode selection reg[0200h] bits 9-8 display mode 00b main window only 01b main window and pip + 10b reserved 11b main window and pip + with overlay table 10-27: lut2 (pip + window) color mode selection reg[0200h] bits 3-2 color depth lut2 bypass enable color 00b 8 bpp 0 lut2 color format 1 data is handled as follows: r_data={r2, r1, r0, r2, r2, r2, r2, r2} g_data={g2, g1, g0, g2, g2, g2, g2, g2} b_data={b1, b0, b1, b1, b1, b1, b1, b1} 01b 16 bpp 0 lut2 color format 1 data is handled as follows: r_data={r4, r3, r2, r1, r0, r4, r4, r4} g_data={g5, g4, g3, g2, g1, g0, g5, g5} b_data={b4, b3, b2, b1,b0, b4, b4, b4} 10b reserved 0 reserved 1 11b reserved 0 reserved 1 free datasheet http:///
page 164 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 1-0 main window bits-per-pixel select bits[1:0] these bits determine the color depth for the main window. for more information, see section 13, ?display data formats? on page 295. bits 15-13 active lcd port status bits[2:0] (read only) these bits indicate the selected output port is active. before sending any commands, parameters, or image data to the port, confirm that the desired port is active. note these bits are read only and are only changed using the lcd output port select bits 2-0 (reg[0202h] bits 12-10). table 10-28: lut1 (main window) color mode selection reg[0200h] bits 1-0 color depth lut1 bypass enable color 00b 8 bpp 0 lut1 color format 1 data is handled as follows: r_data={r2, r1, r0, r2, r2, r2, r2, r2} g_data={g2, g1, g0, g2, g2, g2, g2, g2} b_data={b1, b0, b1, b1, b1, b1, b1, b1} 01b 16 bpp 0 lut1 color format 1 data is handled as follows: r_data={r4, r3, r2, r1, r0, r4, r4, r4} g_data={g5, g4, g3, g2, g1, g0, g5, g5} b_data={b4, b3, b2, b1,b0, b4, b4, b4} 10b reserved 0 reserved 1 11b reserved 0 reserved 1 reg[0202h] display mode setting register 1 default = 0000h read/write active lcd port status bits 2-0 (ro) n/a lcd output port select bits 2-0 sw video invert display blank 15 14 13 12 11 10 9 8 pip + window mirror enable reserved pip+ window swivelview mode select bits 1-0 main window mirror enable n/a main window swivelview mode select bits 1-0 76543 210 table 10-29: active lcd port status reg[0202h] bits 15-13 active lcd port 000b all off 001b lcd1 010b lcd2 011b - 111b reserved free datasheet http:///
epson research and development page 165 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 11-10 lcd output port select bits [2:0] these bits specify the valid output port. changes to these bits take effect after the end of the current frame. the auto transfer bits (reg[003ch] bit 0) must be cleared before changing these bits. bit 9 software video invert this bit determines whether the rgb type panel data output (fpdat[17:0]) is inverted or left unchanged (normal). this bit has an effect when the display is active and when the display is blanked (see reg[0202h] bit 8). for a summary, see table 10-31: ?lcd inter- face data output selection?. when this bit = 0, the panel data output is left unchanged (normal). when this bit = 1, the panel data output is inverted. note if the software video invert bit is set to 1 when configured for an 8-bit parallel panel, the fpdat[15:8] pins will toggle. bit 8 display blank this bit blanks the display of rgb type panels by disabling the display pipe and forcing all data outputs (fpdat[17:0]) low (or high). for a summary, see table 10-31: ?lcd interface data output selection?. when this bit = 0, the display is active. when this bit = 1, display is blanked and all data outputs are forced low or high based on the setting of the software video invert bit (reg[0202h] bit 9). note for further details, see table 5-13: ?lcd interface pin mapping,? on page 46. bit 7 pip + window mirror enable this bit controls the mirror display function for the pip + window. mirror display is inde- pendently controlled for the pip + window and the main window (see reg[0202h] bit 3). when this bit = 0, mirror display for the pip + window is disabled. when this bit = 1, mirror display for the pip + window is enabled. bit 6 reserved the default value for this bit is 0. table 10-30: lcd output port selection reg[0202h] bits 11-10 lcd output port 00b all off 01b lcd1 10b lcd2 11b reserved table 10-31: lcd interface data output selection reg[0202h] bit 8 reg[0202h] bit 9 lcd interface data output 0 0normal 1 inverted 1 0 forced low 1 forced high free datasheet http:///
page 166 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 5-4 pip+ window swivelview mode select bits[1:0] these bits select the swivelview mode of the pip + window. the swivelview mode (ori- entation) of the pip + window is independently controlled for the pip + window and the main window (see bits 1-0). swivelview is a counter-clockwise hardware rotation of the displayed image. for more information on swivelview, see section 14, ?swivelview?? on page 310. bit 3 main window mirror enable this bit controls the mirror display function for the main window. mirror display is inde- pendently controlled for the pip + window (bit 7) and the main window. when this bit = 0, mirror display for the main window is disabled. when this bit = 1, mirror display for the main window is enabled. bits 1-0 main window swivelview mode select bits[1:0] these bits select the swivelview mode of the main window. the swivelview mode (ori- entation) of the main window is independently controlled for the main window and the pip + window (see bits 5-4). swivelview is a counter-clockwise hardware rotation of the displayed image. for more information on swivelview, see section 14, ?swivelview?? on page 310. table 10-32: pip+ window swivelview mode selection reg[0202h] bits 5-4 swivelview mode 00b 0 (normal) 01b 90 10b 180 11b 270 table 10-33: main window swivelview mode selection reg[0202h] bits 1-0 swivelview mode 00b 0 (normal) 01b 90 10b 180 11b 270 free datasheet http:///
epson research and development page 167 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 7-0 transparent overlay key color red data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the red color component of the transparent overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bits 7-0 transparent overlay key color green data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the green color component of the transparent overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0204h] transparent overlay key color red data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 transparent overlay key color red data bits 7-0 76543210 reg[0206h] transparent overlay key color green data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 transparent overlay key color green data bits 7-0 76543210 free datasheet http:///
page 168 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 7-0 transparent overlay key color blue data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the blue color component of the transparent overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0212h] bits 2-0 reg[0210h] bits 15-0 main window display start address bits [18:0] these bits specify the main window starting address for the lcd image in the display buffer. at a color depth of 8 bpp, this register is incremented in 8-bit steps. at 16 bpp, this register should be incremented by 16-bit steps. 16 bpp pixel data should be mapped from even memory addresses, and this register should be set to an even number. reg[0212h] bit 2 reserved the default value for this bit is 0. reg[0208h] transparent overlay key color blue data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 transparent overlay key color blue data bits 7-0 76543210 reg[0210h] main window display start address register 0 default = 0000h read/write main window display start address bits 15-8 15 14 13 12 11 10 9 8 main window display start address bits 7-0 76543210 reg[0212h] main window display start address register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved main window display start address bits 17-16 7 6 5 4 3210 free datasheet http:///
epson research and development page 169 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 main window start address status (read only) when double buffer mode is disabled (reg[0200h] bit 12 = 0), this bit indicates the cur- rent main window frame status. this bit is updated only after the main window display start address has been changed. when this bit = 1, the current frame is using the latest main window display start address values (reg[0210h] - reg[0212h]. when this bit = 0, the next frame will use the latest main window display start address values (reg[0210h] - reg[0212h]). when double buffer mode is enabled (reg[0200h] bit 12 = 1) and the main window is used for the front buffer (reg[0200h] bit 13 = 1), this bit indicates which buffer is currently displayed. when this bit = 0, the back buffer as defined by the back buffer display start address registers (reg[022ah] - reg[022ch]) is being displayed. when this bit = 1, the front buffer which corresponds to the main window area (reg[0210h] - reg[0212h]) is being displayed. reg[0214h] main window start address status register default = 0001h read only n/a 15 14 13 12 11 10 9 8 n/a main window start address status 7 6 5 4 3 2 10 free datasheet http:///
page 170 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 13 main window vertical pixel doubling enable this bit controls the pixel doubling feature for the vertical dimension or height of the panel (i.e. 160 pixel high data doubles for a 320 pixel high panel). when this bit = 0, there is no hardware effect. when this bit = 1, pixel doubling in the vertical dimension (height) is enabled. when vertical pixel doubling of the main window is enabled, the main window display start address must be adjusted according to the selected swivelview mode (see reg[0202h] bits 1-0) using the following formulas. for swivelview 0 address = 0 for swivelview 90 address = (main window height - (bpp/8)) for swivelview 180 address = ((main window height - 1) x (main window width)) - (bpp/8) for swivelview 270 address = main window line offset x ((main window width 2) - 1 bit 12 main window horizontal pixel doubling enable this bit controls the pixel doubling feature for the horizontal dimension or width of the panel (i.e. 160 pixel wide data doubles for a 320 pixel wide panel) when this bit = 0, there is no hardware effect. when this bit = 1, pixel doubling in the horizontal dimension (width) is enabled. when horizontal pixel doubling of the main window is enabled, the main window display start address must be adjusted according to the selected swivelview mode (see reg[0202h] bits 1-0) using the following formulas. for swivelview 0 address = 0 for swivelview 90 address = (main window height - (bpp/8)) for swivelview 180 address = ((main window height - 1) x (main window width)) - (bpp/8) for swivelview 270 address = main window line offset x ((main window width 2) - 1 reg[0216h] main window line address offset register default = 0000h read/write n/a main window vertical pixel doubling enable main window horizontal pixel doubling enable main window line address offset bits 11-8 15 14 13 12 11 10 9 8 main window line address offset bits 7-0 76543210 free datasheet http:///
epson research and development page 171 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 11-0 main window line address offset bits [11:0] these bits specify the offset from the beginning of one display line to the beginning of the next display line in the memory used for the main window. at a color depth of 8 bpp, these bits should be incremented by 8-bit steps. at 16 bpp, these bits should be incremented by 16-bit steps. 16 bpp pixel data should be mapped from even memory addresses, and these bits should be set to an even number. calculate the line address offset as follows (valid for both pixel doubling enabled and disabled). reg[0216h] bits 11-0 = line width in pixels x bpp 8 reg[021ah] bits 1-0 reg[0218h] bits 15-0 pip + display start address bits [17:0] these bits specify the pip+ window starting address for the lcd image in the display buffer. when the pip+ function is disabled (reg[0200h] bits 9-8 = 00b), this register is ignored. at a color depth of 8 bpp, this register is incremented in 8-bit steps. at 16 bpp, this register should be incremented by 16-bit steps. 16 bpp pixel data should be mapped from even memory addresses, and this register should be set to an even number. at 32 bpp, this register should be incremented by 32-bit steps. reg[021ah] bit 2 reserved the default value for this bit is 0. reg[0218h] pip + display start address register 0 default = 0000h read/write pip + display start address bits 15-8 15 14 13 12 11 10 9 8 pip + display start address bits 7-0 76543210 reg[021ah] pip + display start address register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved pip + display start address bits 17-16 7 6 5 4 3210 free datasheet http:///
page 172 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 pip + window start address status (read only) when double buffer mode is disabled (reg[0200h] bit 12 = 0), this bit indicates the cur- rent pip + window frame status. this bit is updated only after the pip + window display start address has been changed. when this bit = 0, the next frame will use the latest pip + window display start address values (reg[0218h] - reg[021ah]). when this bit = 1, the current frame is using the latest pip + window display start address values (reg[0218h] - reg[021ah]. when double buffer mode is enabled (reg[0200h] bit 12 = 1) and the pip + window is used for the front buffer (reg[0200h] bit 13 = 0), this bit indicates which buffer is currently displayed. when this bit = 0, the back buffer as defined by the back buffer display start address registers (reg[022ah] - reg[022ch]) is being displayed. when this bit = 1, the front buffer which corresponds to the pip + window area (reg[0218h] - reg[021ah]) is being displayed. reg[021ch] pip + window start address status register default = 0001h read only n/a 15 14 13 12 11 10 9 8 n/a pip + window start address status 7 6 5 4 3 2 10 free datasheet http:///
epson research and development page 173 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 13 pip + window pixel doubling vertical enable this bit controls the pixel doubling feature for the vertical dimension or height of the panel (i.e. 160 pixel high data doubles for a 320 pixel high panel). when this bit = 0, there is no hardware effect. when this bit = 1, pixel doubling in the vertical dimension (height) is enabled. when vertical pixel doubling of the pip + window is enabled, the pip + window display start address must be adjusted according to the selected swivelview mode (see reg[0202h] bits 5-4) using the following formulas. for swivelview 0 address = 0 for swivelview 90 address = (pip + window height - (bpp/8)) for swivelview 180 address = ((pip + window height - 1) x (pip + window width)) - (bpp/8) for swivelview 270 address = pip + window line offset x ((pip + window width 2) - 1 bit 12 pip + window pixel doubling horizontal enable this bit controls the pixel doubling feature for the horizontal dimension or width of the panel (i.e. 160 pixel wide data doubles for a 320 pixel wide panel) when this bit = 0, there is no hardware effect. when this bit = 1, pixel doubling in the horizontal dimension (width) is enabled. when horizontal pixel doubling of the pip + window is enabled, the pip + window display start address must be adjusted according to the selected swivelview mode (see reg[0202h] bits 5-4) using the following formulas. for swivelview 0 address = 0 for swivelview 90 address = (pip + window height - (bpp/8)) for swivelview 180 address = ((pip + window height - 1) x (pip + window width)) - (bpp/8) for swivelview 270 address = pip + window line offset x ((pip + window width 2) - 1 reg[021eh] pip + window line address offset register default = 0000h read/write n/a pip + window pixel doubling vertical enable pip + window pixel doubling horizontal enable pip + window line address offset bits 11-8 15 14 13 12 11 10 9 8 pip + window line address offset bits 7-0 765 4 3210 free datasheet http:///
page 174 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 11-0 pip + window line address offset bits [11:0] this register specifies the offset from the beginning of one display line to the beginning of the next display line in the memory of the pip + window. at a color depth of 8 bpp, these bits should be incremented by 8-bit steps. at 16 bpp, these bits should be incremented by 16-bit steps. 16 bpp pixel data should be mapped from even memory addresses, and these bits should be set to an even number. calculate the line address offset as follows (valid for both pixel doubling enabled and disabled). reg[021eh] bits 11-0 = line width in pixels x bpp 8 note when the camera image is being displayed in the pip + window, the pip + window size must equal the resulting camera frame dimensions after it has been sized and scaled by the resizer. bits 9-0 pip + window x start position bits [9:0] these bits determine the x start position of the pip + window in relation to the origin of the panel (in pixels). note when the camera image is being displayed in the pip + window, the pip + window size must equal the resulting camera frame dimensions after it has been sized and scaled by the resizer. bits 9-0 pip + window y start position bits [9:0] these bits determine the y start position of the pip + window in relation to the origin of the panel (in pixels). reg[0220h] pip + x start positions register default = 0000h read/write n/a pip + x start position bits 9-8 15 14 13 12 11 10 9 8 pip + x start position bits 7-0 76543210 reg[0222h] pip + y start positions register default = 0000h read/write n/a pip + y start position bits 9-8 15 14 13 12 11 10 9 8 pip + y start position bits 7-0 76543210 free datasheet http:///
epson research and development page 175 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 9-0 pip + window x end position bits [9:0] these bits determine the x end position of the pip + window in relation to the origin of the panel (in pixels). note these bits must be set such that the following formula is valid. reg[0224h] bits 9-0 < horizontal display period note when the camera image is being displayed in the pip + window, the pip + window size must equal the resulting camera frame dimensions after it has been sized and scaled by the resizer. bits 9-0 pip + window y end position bits [9:0] these bits determine the y end position of the pip + window in relation to the origin of the panel (in pixels). note these bits must be set such that the following formula is valid. reg[0226h] bits 9-0 < vertical display period note when the camera image is being displayed in the pip + window, the pip + window size must equal the resulting camera frame dimensions after it has been sized and scaled by the resizer. reg[0228h] is reserved this register is reserved and should not be written. reg[0224h] pip + x end positions register default = 0000h read/write n/a pip + x end position bits 9-8 15 14 13 12 11 10 9 8 pip + x end position bits 7-0 76543210 reg[0226h] pip + y end positions register default = 0000h read/write n/a pip + y end position bits 9-8 15 14 13 12 11 10 9 8 pip + y end position bits 7-0 76543210 free datasheet http:///
page 176 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[022ch] bits 1-0 reg[022ah] bits 15-0 back buffer display start address bits [17:0] these bits specify the back buffer window starting address for the lcd image in the display buffer. when the double buffer function is disabled (reg[0200h] bit 12 = 0), this register is ignored. reg[022ch] bit 2 reserved the default value for this bit is 0. bit 15 yuv/rgb converter bypass enable when yuv/rgb converter (yrc) bypass mode is enabled, yuv data from the camera interface or jpeg decoder, or host goes directly into the internal memory. when the yrc is enabled (bypass mode is disabled), incoming yuv data is converted to rgb format and stored in the display buffer to be displayed by the lcd panel. when this bit = 0, yuv/rgb converter bypass mode is disabled (default). when this bit = 1, yuv/rgb converter bypass mode is enabled. note the yuv/rgb converter swaps the incoming byte data when it is disabled. to change the yuv data back to normal, set the yrc output data format select bit (reg[0240h] bit 8) to 1. disabling the yrc is useful for cameras that can output rgb data. reg[022ah] back buffer display start address register 0 default = 0000h read/write buck buffer display start address bits 15-8 15 14 13 12 11 10 9 8 back buffer display start address bits 7-0 76543210 reg[022ch] back buffer display start address register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved back buffer display start address bits 17-16 7 6 5 4 3210 reg[0240h] yuv/rgb translate mode register default = 0405h read/write yuv/rgb converter bypass enable yuv/rgb converter reset uv fix bits 1-0 yrc output bpp select bits 1-0 n/a yuv output data format select 15 14 13 12 11 10 98 reserved yuv/rgb rectangular write mode enable frame buffer writing mode select yuv input data type select n/a yuv/rgb transfer mode bits 2-0 7654 3210 free datasheet http:///
epson research and development page 177 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 14 yuv/rgb converter reset this bit is resets the yuv/rgb converter (yrc). it has no effect on the yrc registers. the yrc should be reset after any changes are made to the resizer operation registers (reg[0930h]-[096eh] and before performing a memory image jpeg encode operation. when this bit is set to 0, the yrc is available for use. when this bit is set to 1, the yuv/rgb converter is reset. this bit must be set back to 0 before the yuv/rgb converter can be used again. bits 13-12 uv fix select bits [1:0] these bits control the uv input to the yuv/rgb converter (yrc). the setting of these bits has an effect on the uv data even when the yrc is disabled (reg[0240h] bit 15 = 1).. bits 11-10 yrc output bpp select bits [1:0] these bits specify the color depth in bits-per-pixel (bpp) for the yuv/rgb converter out- put. bit 8 yrc output data format select this bit selects the output data format of the yuv/rgb converter (yrc) when it is dis- abled (reg[0240h] bit 15 = 1). this bit has no effect when the yrc is enabled (reg[0240h] bit 15 = 0). when this bit = 0, vyuy format is selected. see table 10-36: ?vyuy output data for- mat (reg[0240h] bit 8 = 0),? on page 178. when this bit = 1, yuyv format is selected. see table 10-37: ?yuyv output data for- mat select (reg[0240h] bit 8 = 1),? on page 178. table 10-34: uv fix selection reg[0240h] bits 13-12 uv input to the yuv/rgb converter 00b original u data, original v data 01b u data = reg[024ah] bits 15-8, original v data 10b original u data, v data = reg[024ah] bits 7-0 11b u data = reg[024ah] bits 15-8, v data = reg[024ah] bits 7-0 table 10-35: yuv/rgb converter output bpp selection reg[0240h] bits 11-10 yuv/rgb converter output bpp 00b 16 bpp 01b (default) 10b reserved 11b reserved free datasheet http:///
page 178 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 7 reserved the default value for this bit is 0. table 10-36: vyuy output data format (reg[0240h] bit 8 = 0) cycle count 1 2 3 4 ... 2n+1 2n+2 d15 v 0 7 u 0 7 v 2 7 u 2 7 ... v 2n 7 u 2n 7 d14 v 0 6 u 0 6 v 2 6 u 2 6 ... v 2n 6 u 2n 6 d13 v 0 5 u 0 5 v 2 5 u 2 5 ... v 2n 5 u 2n 5 d12 v 0 4 u 0 4 v 2 4 u 2 4 ... v 2n 4 u 2n 4 d11 v 0 3 u 0 3 v 2 3 u 2 3 ... v 2n 3 u 2n 3 d10 v 0 2 u 0 2 v 2 2 u 2 2 ... v 2n 2 u 2n 2 d9 v 0 1 u 0 1 v 2 1 u 2 1 ... v 2n 1 u 2n 1 d8 v 0 0 u 0 0 v 2 0 u 2 0 ... v 2n 0 u 2n 0 d7 y 1 7 y 0 7 y 3 7 y 2 7 ... y 2n+1 7 y 2n 7 d6 y 1 6 y 0 6 y 3 6 y 2 6 ... y 2n+1 6 y 2n 6 d5 y 1 5 y 0 5 y 3 5 y 2 5 ... y 2n+1 5 y 2n 5 d4 y 1 4 y 0 4 y 3 4 y 2 4 ... y 2n+1 4 y 2n 4 d3 y 1 3 y 0 3 y 3 3 y 2 3 ... y 2n+1 3 y 2n 3 d2 y 1 2 y 0 2 y 3 2 y 2 2 ... y 2n+1 2 y 2n 2 d1 y 1 1 y 0 1 y 3 1 y 2 1 ... y 2n+1 1 y 2n 1 d0 y 1 0 y 0 0 y 3 0 y 2 0 ... y 2n+1 0 y 2n 0 table 10-37: yuyv output data format select (reg[0240h] bit 8 = 1) cycle count 1 2 3 4 ... 2n+1 2n+2 d15 y 0 7 y 1 7 y 2 7 y 3 7 ... y 2n 7 y 2n+1 7 d14 y 0 6 y 1 6 y 2 6 y 3 6 ... y 2n 6 y 2n+1 6 d13 y 0 5 y 1 5 y 2 5 y 3 5 ... y 2n 5 y 2n+1 5 d12 y 0 4 y 1 4 y 2 4 y 3 4 ... y 2n 4 y 2n+1 4 d11 y 0 3 y 1 3 y 2 3 y 3 3 ... y 2n 3 y 2n+1 3 d10 y 0 2 y 1 2 y 2 2 y 3 2 ... y 2n 2 y 2n+1 2 d9 y 0 1 y 1 1 y 2 1 y 3 1 ... y 2n 1 y 2n+1 1 d8 y 0 0 y 1 0 y 2 0 y 3 0 ... y 2n 0 y 2n+1 0 d7 u 0 7 v 0 7 u 2 7 v 2 7 ... u 2n 7 v 2n+1 7 d6 u 0 6 v 0 6 u 2 6 v 2 6 ... u 2n 6 v 2n+1 6 d5 u 0 5 v 0 5 u 2 5 v 2 5 ... u 2n 5 v 2n+1 5 d4 u 0 4 v 0 4 u 2 4 v 2 4 ... u 2n 4 v 2n+1 4 d3 u 0 3 v 0 3 u 2 3 v 2 3 ... u 2n 3 v 2n+1 3 d2 u 0 2 v 0 2 u 2 2 v 2 2 ... u 2n 2 v 2n+1 2 d1 u 0 1 v 0 1 u 2 1 v 2 1 ... u 2n 1 v 2n+1 1 d0 u 0 0 v 0 0 u 2 0 v 2 0 ... u 2n 0 v 2n+1 0 free datasheet http:///
epson research and development page 179 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 6 yuv/rgb rectangular write mode enable when this bit = 0, continuous write mode is selected. in continuous write mode, data is written to the frame buffer continuously based on the yuv/rgb converter frame buffer write start address registers (reg[0242h]-[0244h]). when this bit = 1, rectangular write mode is selected. in rectangular write mode, data is written based on the x pixel size register (reg[024ch]) and the frame buffer line address offset register (reg[024eh]). note yuv/rgb rectangular write mode may only be enabled when single buffer writing mode is selected (reg[0240h] bit 5 = 0). bit 5 frame buffer writing mode select this bit determines the write mode used by the yrc when writing yuv data to the frame buffer. when this bit = 0, single buffer write mode is selected. in single buffer write mode, frames of data are written only to the memory section defined by reg[0244h] - reg[0242h]. when this bit = 1, double buffer write mode is selected. in double buffer write mode, frames of data are written alternately between the memory section defined by reg[0244h] - reg[0242h] and the the memory section defined by reg[0248h] - reg[0246h]. this mode can be used with double buffer mode (reg[0200h] bit 12 = 1) to prevent ?tearing? of the camera image for fast moving images. bit 4 yrc input data type select this bit specifies the data type of the yuv input to the yuv to rgb converter (yrc). bits 2-0 yuv/rgb transfer mode bits [2:0] these bits specify the yuv/rgb transfer mode. recommended settings are provided for various specifications.. table 10-38: yuv data type selection reg[0240h] bit 4 yrc input data type yrc input data range 0 yuv offset 0 y 255 -128 u 127 -128 v 127 1 ycbcr offset 16 y 235 -113 u 112 -113 v 112 table 10-39: yuv/rgb transfer mode selection reg[0240h] bits 2-0 yuv/rgb specification 000b reserved 001b recommended for itu-r bt.709 010b reserved 011b reserved 100b recommended for itu-r bt.470-6 system m 101b (default) recommended for itu-r bt.470-6 system b, g (recommended for itu-r bt.601-5) 110b smpte 170m 111b smpte 240m(1987) free datasheet http:///
page 180 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[0244h] bits 1-0 reg[0242h] bits 15-0 yuv/rgb converter write start address 0 bits [17:0] these bits determine the start address where the yuv/rgb converter writes data. the yuv/rgb converter writes data to the display buffer in 32-bit blocks, therefore bits 1-0 of reg[0242h] must be set to 00b. reg[0244h] bit 2 reserved the default value for this bit is 0. reg[0248h] bits 2-0 reg[0246h] bits 15-0 yuv/rgb converter write start address 1 bits [18:0] these bits determine the start address for data input from the camera interface and for jpeg decoded images. this register value is valid when frame buffer writing mode select bit (reg[0240h] bit 5) is set for double buffer writing mode. reg[0248h] bit 2 reserved the default value for this bit is 0. reg[0242h] yuv/rgb converter write start address 0 register 0 default = 0000h read/write yuv/rgb converter write start address 0 bits 15-8 15 14 13 12 11 10 9 8 yuv/rgb converter write start address 0 bits 7-0 76543210 reg[0244h] yuv/rgb converter write start address 0 register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved yuv/rgb converter write start address bits 18-16 7 6 5 4 3210 reg[0246h] yuv/rgb converter write start address 1 register 0 default = 0000h read/write yuv/rgb converter write start address 1 bits 15-8 15 14 13 12 11 10 9 8 yuv/rgb converter write start address 1 bits 7-0 76543210 reg[0248h] yuv/rgb converter write start address 1 register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved yuv/rgb converter write start address 1 bits 17-16 7 6 5 4 3210 free datasheet http:///
epson research and development page 181 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 15-8 u data fix bits [7:0] these bits only have an effect when the uv fix select bits are set to 01b or 11b (reg[0240h] bits 13-12 = 01b or 11b). the u data input of the yuv/rgb converter data is fixed to the value of these bits. bits 7-0 v data fix bits [7:0] these bits only have an effect when the uv fix select bits are set to 10b or 11b (reg[0240h] bits 13-12 = 10b or 11b). the v data input of yuv/rgb converter data is fixed to the value of these bits. bits 10-0 yrc rectangular pixel width bits [10:0] these bits specify the horizontal pixel size of the data being written when the yuv/rgb converter (yrc) is configured for rectangular write mode (reg[0240h] bit 6 = 1). for a color depth of 16 bpp, it specifies an even number of pixels (only bits 9-1 are used). bits 11-0 yrc rectangular line address offset bits [11:0] these bits specify the number of pixels from the beginning of the current display line to the beginning of the next line when the yuv/rgb converter (yrc) is configured for rectangular write mode (reg[0240h] bit 6 = 1). for a color depth of 16 bpp, it specifies an even number of pixels (only bits 11-1 are used). when the yuv/rgb converter is disabled, it specifies every pixel (all bits 11-0 are used). reg[0268h] is reserved this register is reserved and should not be written. reg[0280h] is reserved this register is reserved and should not be written. reg[024ah] uv data fix register default = 0000h read/write u data fix bits 7-0 15 14 13 12 11 10 9 8 v data fix bits 7-0 76543210 reg[024ch] yrc rectangle pixel width register default = 0000h read/write n/a yrc rectangular pixel width bits 10-8 15 14 13 12 11 10 9 8 yrc rectangular pixel width bits 7-0 76543210 reg[024eh] yrc rectangular line address offset register default = 0000h read/write n/a yrc rectangular line address offset bits 11-8 15 14 13 12 11 10 9 8 yrc rectangular line address offset bits 7-0 76543210 free datasheet http:///
page 182 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.9 gpio registers bits 15-4 reserved the default value for these bits is 0. bits 3-0 gpio[3:0] pin io configuration when the gpio pins (gpio[3:0]) are configured as inputs at reset# (cnf1 = 1), these bits can be used to change individual gpio pins between inputs/outputs. when the gpio pins are configured as outputs at reset# (cnf1 = 0), these bits are ignored and the gpio pins are always outputs. when a bit = 0 (default), the corresponding gpio pin is configured as an input pin. when a bit = 1, the corresponding gpio pin is configured as an output pin. bits 15-4 reserved the default value for these bits is 0. bits 3-0 gpio[3:0] pin input enable these bits are used to enable the input function of each gpio pin. they must be changed to a 1 after power-on reset to enable the input function of the corresponding gpio pin. when a bit = 0 (default), the input function for the corresponding gpio pin is disabled. when a bit = 1, the input function for the corresponding gpio pin is enabled. note when the gpio pins are configured as outputs at reset# (cnf1 = 0), the gpio pins are always outputs and these bits have no effect. reg[0300h] gpio status and control register 0 default = 0000h read/write reserved 15 14 13 12 11 10 9 8 reserved gpio3 config gpio2 config gpio1 config gpio0 config 76543210 reg[0304h] gpio status and control register 3 default = 0000h read/write reserved 15 14 13 12 11 10 9 8 reserved gpio3 input enable gpio2 input enable gpio1 input enable gpio0 input enable 76543210 free datasheet http:///
epson research and development page 183 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 15-4 reserved the default value for these bits is fffh. bits 3-0 gpio[3:0] pull-down control all gpio pins have internal pull-down resistors. these bits individually control the state of the pull-down resistors. when a bit = 0, the pull-down resistor for the associated gpio pin is inactive. when a bit = 1, the pull-down resistor for the associated gpio pin is active (default). bits 15-4 reserved the default value for these bits is 0. bits 3-0 gpio[3:0] pin io status when gpiox is configured as an output (see reg[0300h]), writing a 0 to this bit drives the corresponding gpiox low and writing a 1 to this bit drives the corresponding gpiox high. when gpiox is configured as an input (see reg[0300h]), a read from this bit returns the status of the corresponding gpiox. note to read the status of a gpio pin configured as an input, the gpio pin must first have it?s input function enabled using reg[0304h]. reg[0308h] gpio pull down control register 0 default = ffffh read/write reserved 15 14 13 12 11 10 9 8 reserved gpio3 pull-down control gpio2 pull-down control gpio1 pull-down control gpio0 pull-down control 76543210 reg[030ch] gpio status and control register 4 default = 0000h read/write reserved 15 14 13 12 11 10 9 8 reserved gpio3 status gpio2 status gpio1 status gpio0 status 76543210 free datasheet http:///
page 184 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.10 overlay registers bit 7-0 average overlay key color red data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the red color component of the average overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 average overlay key color green data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the green color component of the average overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0310h] average overlay key color red data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 average overlay key color red data bits 7-0 76543210 reg[0312h] average overlay key color green data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 average overlay key color green data bits 7-0 76543210 free datasheet http:///
epson research and development page 185 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 7-0 average overlay key color blue data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the blue color component of the average overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 and overlay key color red data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the red color component of the and overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0314h] average overlay key color blue data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 average overlay key color blue data bits 7-0 76543210 reg[0316h] and overlay key color red data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 and overlay key color red data bits 7-0 76543210 free datasheet http:///
page 186 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 7-0 and overlay key color green data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the green color component of the and overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 and overlay key color blue data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the blue color component of the and overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. if this function doesn?t apply to a display area, it still prevents a lower pri- ority function from taking effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0318h] and overlay key color green data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 and overlay key color green data bits 7-0 76543210 reg[031ah] and overlay key color blue data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 and overlay key color blue data bits 7-0 76543210 free datasheet http:///
epson research and development page 187 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 7-0 or overlay key color red data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the red color component of the or overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 or overlay key color green data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the green color component of the or overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[031ch] or overlay key color red data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 or overlay key color red data bits 7-0 76543210 reg[031eh] or overlay key color green data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 or overlay key color green data bits 7-0 76543210 free datasheet http:///
page 188 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 7-0 or overlay key color blue data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the blue color component of the or overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 inv overlay key color red data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the red color component of the inv overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0320h] or overlay key color blue data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 or overlay key color blue data bits 7-0 76543210 reg[0322h] inv overlay key color red data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 inv overlay key color red data bits 7-0 76543210 free datasheet http:///
epson research and development page 189 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 7-0 inv overlay key color green data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the green color component of the inv overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 7-0 inv overlay key color blue data bits [7:0] these bits only have an effect when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b). these bits set the blue color component of the inv overlay key color. for more information on overlays, see section 15.1, ?overlay display? on page 316. note if lut bypass mode is enabled (see reg[0200h] bits 5-4), the key color bits must be expanded to a full 8 bits using the bit cover method in section 13.3.2, ?bit cover when lut bypassed? on page 298. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0324h] inv overlay key color green data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 inv overlay key color green data bits 7-0 76543210 reg[0326h] inv overlay key color blue data register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 inv overlay key color blue data bits 7-0 76543210 free datasheet http:///
page 190 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 15 overlay pip + window bit shift this bit only has an effect if the display mode select bits are set for pip + with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the pip + window pixel data is normal. when this bit = 1, the pip + window is pixel data is bit shifted to the right by 1 bit. bits 13 overlay main window bit shift this bit only has an effect if the display mode select bits are set for pip+ with overlay (reg[0200h] bits 9-8 = 11b) and any overlay key color enable bit is set to 1. for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the main window pixel data is normal. when this bit = 1, the main window pixel data is bit shifted to the right by 1 bit. bit 4 inv overlay key color enable this bit only has an effect if the display mode select bits are set for pip+ with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the inv overlay key color function is disabled. when this bit = 1, the inv overlay key color function is enabled. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 3 or overlay key color enable this bit only has an effect if the display mode select bits are set for pip+ with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the or overlay key color function is disabled. when this bit = 1, the or overlay key color function is enabled. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. reg[0328h] overlay miscellaneous register default = 0000h read/write overlay pip+ window bit shift n/a overlay main window bit shift n/a 15 14 13 12 11 10 9 8 n/a inv overlay key color enable or overlay key color enable and overlay key color enable average overlay key color enable transparent overlay key color enable 7 6 543210 free datasheet http:///
epson research and development page 191 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 2 and overlay key color enable this bit only has an effect if the display mode select bits are set for pip+ with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the and overlay key color function is disabled. when this bit = 1, the and overlay key color function is enabled. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 1 average overlay key color enable this bit only has an effect if the display mode select bits are set for pip + with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the average overlay key color function is disabled. when this bit = 1, the average overlay key color function is enabled. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. bit 0 transparent overlay key color enable this bit only has an effect if the display mode select bits are set for pip + with overlay (reg[0200h] bits 9-8 = 11b). for more information on the overlay function, see section 15.1, ?overlay display? on page 316. when this bit = 0, the transparent overlay key color function is disabled. when this bit = 1, the transparent overlay key color function is enabled. note if more than one overlay function is enabled, only the function with the highest priority takes effect. however, if this function doesn?t apply to a display area, the next lower pri- ority function takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. free datasheet http:///
page 192 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.11 lut1 (main window) registers figure 10-2: lut1 mapping bits 15-8 lut1 (main window) green data bits [7:0] these bits are used to set the lut1 green data. there are 256 entries in lut1 from 0400h to 07fch. lut1 is used for the main window. bits 7-0 lut1 (main window) red data bits [7:0] these bits are used to set the lut1 red data. there are 256 entries in lut1 from 0400h to 07fch. lut1 is used for the main window. bits 7-0 lut1 (main window) blue data bits [7:0] these bits are used to set the lut1 blue data. there are 256 entries in lut1 from 0402h to 07feh. lut1 is used for the main window. reg[0400 - 07fch] lut1 data register 0 default = not applicable read/write lut1 green data bits 7-0 15 14 13 12 11 10 9 8 lut1 red data bits 7-0 76543210 reg[0402 - 07feh] lut1 data register 1 default = not applicable read/write n/a 15 14 13 12 11 10 9 8 lut1 blue data bits 7-0 76543210 0400h ... 0402h 0404h green 0 green 1 red 0 red 1 low byte blue 0 n/a ... high byte 07feh n/a blue 255 free datasheet http:///
epson research and development page 193 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.12 lut2 (pip + window) registers figure 10-3: lut2 mapping bits 15-8 lut2 (pip + window) green data bits [7:0] these bits are used to set the lut2 green data. there are 64 entries in lut2 from 0800h to 08fch. lut2 is used for the pip + window. bits 7-0 lut2 (pip + window) red data bits [7:0] these bits are used to set the lut2 red data. there are 64 entries in lut2 from 0800h to 08fch. lut2 is used for the pip + window. bits 7-0 lut2 (pip + window) blue data bits [7:0] these bits are used to set the lut2 blue data. there are 64 entries in lut2 from 0802h to 08feh. lut2 is used for the pip + window. reg[0800 - 08fch] lut2 data register 0 default = not applicable read/write lut2 green data bits 7-0 15 14 13 12 11 10 9 8 lut2 red data bits 7-0 76543210 reg[0802 - 08feh] lut2 data register 1 default = not applicable read/write n/a 15 14 13 12 11 10 9 8 lut2 blue data bits 7-0 76543210 0800h ... 0802h 0804h green 0 green 1 red 0 red 1 low byte blue 0 n/a ... high byte 08feh n/a blue 63 free datasheet http:///
page 194 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.13 resizer operation registers note the resizer registers must not be changed while receiving data from the camera inter- face, jpeg decoder, or host interface. bit 10 resizer frame reduction this bit controls frame reduction in the resizer block. when this bit = 0, the resizer performs no reduction. when this bit = 1, the resizer performs frame reduction by using only every second frame. bit 9 reserved the default value for this bit is 0. bit 8 reserved the default value for this bit is 0. bit 4 reserved the default value for this bit is 0. reg[0930h] global resizer control register default = 0000h read/write n/a resizer frame reduction reserved reserved 15 14 13 12 11 10 9 8 n/a reserved output source select n/a camera display control bits 1-0 7 6 543 210 free datasheet http:///
epson research and development page 195 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 3 output source select this bit selects which resizer outputs data to the yuv/rgb converter (yrc). typically, the view resizer is selected when data comes from the camera interface since jpeg encode dimensions may differ from display dimensions. for jpeg decode and host to S1D13717 yuv mode, the view resizer must be selected. when this bit = 0, the view resizer outputs data to the yrc. when this bit = 1, the capture resizer outputs data to the yrc and the view resizer logic is powered down. note during jpeg encoding, this bit must be set to an active resizer, or the yrc must be dis- abled (reg[0240h] bit 14 = 1). 0: view resizer selected 1: capture resizer selected table 10-40: output source select output source select reg[0930h] bit 3 view resizer enable reg[0940h] bit 0 capture resizer enable reg[0960h] bit 0 to yuv/rgb converter to jpeg line buffer 000?? 001?? 010available? 0 1 1 available available 100?? 1 0 1 available available 110?? 1 1 1 available available free datasheet http:///
page 196 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 1-0 camera display control bits [1:0] these bits control how camera data is displayed when a jpeg encode operation is per- formed (reg[0980h] bits 3-1 = 000b) and when yuv to host mode (jpeg bypass) is enabled (reg[0980h] bits 3-1 = 011b or 111b). . reg[0932h] through reg[093eh] are reserved these registers are reserved and should not be written. table 10-41: camera display control selection reg[0930h] bits 1-0 function 00b jpeg encode: yuv data from the camera interface is continuously written to the display buffer until a jpeg encode operation is performed. when a jpeg encode operation is started (reg[098ah] bit 0 = 1), camera data is no longer written to the display buffer once the next frame is written. after reg[098ah] bit 0 is set to 0, camera data is again written to the display buffer from the next frame. jpeg bypass: yuv data from the camera interface is continuously written to the jpeg fifo and converted yuv data (yuv/rgb converter) is continuously written to the display buffer. 01b jpeg encode: when a jpeg encode operation is started, reg[098a] bit 0 = 1b, only the next frame of camera data is written to the display buffer. when a jpeg encode operation is not enabled, reg[098a] bit 0 = 0b, camera data is not written to the display buffer. jpeg bypass: yuv data from the camera interface is continuously written to the jpeg fifo. when the shutter is enabled, reg[098a] bit 0 = 1b, camera data is written to the display buffer. when the shutter is disabled, reg[098a] bit 0 = 0b, camera data is not written to the display buffer. 10b jpeg encode: data from the camera interface is always written to the display buffer. jpeg bypass: yuv data from the camera interface is continuously written to the jpeg fifo and converted yuv data (yuv/rgb converter) is continuously written to the display buffer. 11b reserved. free datasheet http:///
epson research and development page 197 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential . bit 10 reserved the default value for this bit is 0. bit 7 view resizer software reset (write only) when a 0 is written to this bit, there is no hardware effect. when the resizers are activated by writing a 1 to reg[0940h] bit 0 or reg[0960h] bit 0 and a 1 is written to this bit, the view resizer logic is reset. bit 2 view resizer independent horizontal/vertical scaling enable when this bit = 0, the horizontal and vertical scaling rates are the same. both horizontal and vertical scaling rates are controlled by reg[094ch] bits 5-0. when this bit = 1, the horizontal and vertical scaling rates can be selected independently. horizontal scaling rate is controlled by reg[094ch] bits 5-0 and vertical scaling rate is controlled by reg[094ch] bits 13-8. bit 1 view resizer register update vsync enable when this bit = 0, the view resizer use the new register value immediately. when this bit = 1, the view resizer uses the previous register value until the next camera vsync occurs. bit 0 view resizer enable this bit controls the view resizer logic. when this bit = 0, the view resizer logic is disabled. when this bit = 1, the view resizer logic is enabled. note when this bit and the capture resizer enable bit (reg[0960h] bit 0) are both set to 0, the clock to the resizer block is automatically stopped. reg[0940h] view resizer control register default = 0000h read/write n/a reserved n/a 15 14 13 12 11 10 9 8 view resizer software reset (wo) n/a view resizer independent horizontal/vertical scaling enable view resizer register update vsync enable view resizer enable 7 6 5 4 3210 free datasheet http:///
page 198 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 10 reserved the default value for this bit is 0. bits 9-0 view resizer start x position bits [9:0] these bits determine the x start position for the view resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. bit 10 reserved the default value for this bit is 0. bits 9-0 view resizer start y position bits [9:0] these bits determine the y start position for the view resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. reg[0944h] view resizer start x position register default = 0000h read/write n/a reserved view resizer start x position bits 9-8 15 14 13 12 11 10 9 8 view resizer start x position bits 7-0 76543210 reg[0946h] view resizer start y position register default = 0000h read/write n/a reserved view resizer start y position bits 9-8 15 14 13 12 11 10 9 8 view resizer start y position bits 7-0 76543210 free datasheet http:///
epson research and development page 199 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 10 reserved the default value for this bit is 0. bits 9-0 view resizer end x position bits [9:0] these bits determine the x end position for the view resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. bit 10 reserved the default value for this bit is 0. bits 9-0 view resizer end y position bits [9:0] these bits determine the y end position for the view resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. bits 13-8 view resizer vertical scaling rate bits [5:0] these bits determine the view resizer vertical scaling rate when independent horizon- tal/vertical scaling is enabled (reg[0940h] bit 2 = 1). not all scaling rates are available for all scaling modes (see reg[094eh] bits 1-0). for a summary of the available scaling rate/mode options, see table 10-42: ?view resizer vertical scaling rate selection,? on page 200. reg[0948h] view resizer end x position register default = 027fh read/write n/a reserved view resizer end x position bits 9-8 15 14 13 12 11 10 9 8 view resizer end x position bits 7-0 76543210 reg[094ah] view resizer end y position register default = 01dfh read/write n/a reserved view resizer end y position bits 9-8 15 14 13 12 11 10 9 8 view resizer end y position bits 7-0 76543210 reg[094ch] view resizer operation setting register 0 default = 0101h read/write n/a view resizer vertical scaling rate bits 5-0 15 14 13 12 11 10 9 8 n/a view resizer horizontal scaling rate bits 5-0 7 6543210 free datasheet http:///
page 200 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 10-42: view resizer vertical scaling rate selection reg[094ch] bits 13-8 view resizer vertical scaling rate reg[094eh] bits 1-0 = 00 reg[094eh] bits 1-0 = 01 reg[094eh] bits 1-0 = 10 reg[094eh] bits 1-0 = 11 00 0000b reserved reserved reserved reserved 00 0001b n/a 1/1 1/1 reserved 00 0010b n/a 1/2 1/2 reserved 00 0011b n/a 1/3 1/3 reserved 00 0100b n/a 1/4 1/4 reserved 00 0101b n/a 1/5 1/5 reserved 00 0110b n/a 1/6 1/6 reserved 00 0111b n/a 1/7 1/7 reserved 00 1000b n/a 1/8 1/8 reserved 00 1001b n/a 1/9 1/9 reserved 00 1010b n/a 1/10 1/10 reserved 00 1011b n/a 1/11 1/11 reserved 00 1100b n/a 1/12 1/12 reserved 00 1101b n/a 1/13 1/13 reserved 00 1110b n/a 1/14 1/14 reserved 00 1111b n/a 1/15 1/15 reserved 01 0000b n/a 1/16 1/16 reserved 01 0001b n/a 1/17 1/17 reserved 01 0010b n/a 1/18 1/18 reserved 01 0011b n/a 1/19 1/19 reserved 01 0100b n/a 1/20 1/20 reserved 01 0101b n/a 1/21 1/21 reserved 01 0110b n/a 1/22 1/22 reserved 01 0111b n/a 1/23 1/23 reserved 01 1000b n/a 1/24 1/24 reserved 01 1001b n/a 1/25 1/25 reserved 01 1010b n/a 1/26 1/26 reserved 01 1011b n/a 1/27 1/27 reserved 01 1100b n/a 1/28 1/28 reserved 01 1101b n/a 1/29 1/29 reserved 01 1110b n/a 1/30 1/30 reserved 01 1111b n/a 1/31 1/31 reserved 10 0000b n/a 1/32 1/32 reserved 10 0001b - 11 1111b reserved reserved reserved reserved free datasheet http:///
epson research and development page 201 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 5-0 view resizer horizontal scaling rate bits [5:0] when independent horizontal/vertical scaling is disabled (reg[0940h] bit 2 = 0), these bits determine the vertical and horizontal scaling rate. when independent horizontal/verti- cal scaling is enabled (reg[0940h] bit 2 = 1), these bits only determine the horizontal scaling rate. not all scaling rates are available for all scaling modes (see reg[094eh] bits 1-0). for a summary of the available scaling rate/mode options, see table 10-43: ?view resizer horizontal scaling rate selection,? on page 201. table 10-43: view resizer horizontal scaling rate selection reg[094ch] bits 5-0 view resizer horizontal scaling rate reg[094eh] bits 1-0 = 00 reg[094eh] bits 1-0 = 01 reg[094eh] bits 1-0 = 10 reg[094eh] bits 1-0 = 11 00 0000b reserved reserved reserved reserved 00 0001b n/a 1/1 1/1 reserved 00 0010b n/a 1/2 1/2 reserved 00 0011b n/a 1/3 reserved reserved 00 0100b n/a 1/4 1/4 reserved 00 0101b n/a 1/5 reserved reserved 00 0110b n/a 1/6 reserved reserved 00 0111b n/a 1/7 reserved reserved 00 1000b n/a 1/8 1/8 reserved 00 1001b n/a 1/9 reserved reserved 00 1010b n/a 1/10 reserved reserved 00 1011b n/a 1/11 reserved reserved 00 1100b n/a 1/12 reserved reserved 00 1101b n/a 1/13 reserved reserved 00 1110b n/a 1/14 reserved reserved 00 1111b n/a 1/15 reserved reserved 01 0000b n/a 1/16 1/16 reserved 01 0001b n/a 1/17 reserved reserved 01 0010b n/a 1/18 reserved reserved 01 0011b n/a 1/19 reserved reserved 01 0100b n/a 1/20 reserved reserved 01 0101b n/a 1/21 reserved reserved 01 0110b n/a 1/22 reserved reserved 01 0111b n/a 1/23 reserved reserved 01 1000b n/a 1/24 reserved reserved 01 1001b n/a 1/25 reserved reserved 01 1010b n/a 1/26 reserved reserved 01 1011b n/a 1/27 reserved reserved 01 1100b n/a 1/28 reserved reserved 01 1101b n/a 1/29 reserved reserved 01 1110b n/a 1/30 reserved reserved 01 1111b n/a 1/31 reserved reserved 10 0000b n/a 1/32 1/32 reserved 10 0001b - 11 1111b reserved reserved reserved reserved free datasheet http:///
page 202 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 3-2 reserved the default value for these bits is 0. bits 1-0 view resizer scaling mode bits[1:0] these bits determine the view resizer scaling mode. not all scaling modes are available for all scaling rates. before selecting a scaling mode, set the view resizer vertical scaling rate bits (reg[094eh] bits 13-8) and/or the view resizer horizontal scaling rate bits (reg[094ch] bits 5-0) to a valid scaling rate. enabling a scaling mode with an unsup- ported scaling rate (reserved or n/a) may turn off the view resizer. . bit 7 capture resizer software reset (write only) when a 0 is written to this bit, there is no hardware effect. when the resizers are activated by writing a 1 to reg[940h] bit 0 or reg[0960h] bit 0 and a 1 is written to this bit, the capture resizer logic is reset. bit 2 capture resizer independent horizontal/vertical scaling enable when this bit = 0, the horizontal and vertical scaling rates are the same. both horizontal and vertical scaling rates are controlled by reg[096ch] bits 4-0. when this bit = 1, the horizontal and vertical scaling rates can be selected independently. horizontal scaling rate is controlled by reg[096ch] bits 4-0 and vertical scaling rate is controlled by reg[096ch] bits 12-8. reg[094eh] view resizer operation setting register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved view resizer scaling mode bits 1-0 7 6 5 43210 table 10-44: view resizer scaling mode selection reg[094eh] bits 1-0 view resizer scaling mode 00b no resizer scaling 01b v/h reduction 10b v: reduction, h: average 11b reserved reg[0960h] capture resi zer control register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 capture resizer software reset (wo) n/a capture resizer independent horizontal/vertical scaling enable capture resizer register update vsync enable capture resizer enable 7 6 5 4 3210 free datasheet http:///
epson research and development page 203 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 1 capture resizer register update vsync enable when this bit = 0, the capture resizer use the new register value immediately. when this bit = 1, the capture resizer uses the previous register value until the next cam- era vsync occurs. bit 0 capture resizer enable this bit controls the capture resizer logic. when this bit = 0, the capture resizer logic is disabled. when this bit = 1, the capture resizer logic is enabled. note when this bit and the view resizer enable bit (reg[0940h] bit 0) are both set to 0, the clock to the resizer block is automatically stopped. bit 10 reserved the default value for this bit is 0. bits 9-0 capture resizer start x position bits [9:0] these bits determine the x start position for the capture resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. the following image size limitations must be observed when the jpeg functions (or jpeg bypass) are used. reg[0964h] capture resizer start x position register default = 0000h read/write n/a reserved capture resizer start x position bits 9-0 15 14 13 12 11 10 9 8 capture resizer start x position bits 7-0 76543210 table 10-45: capture resizer limitations yuv format minimum horizontal resolution minimum vertical resolution minimum size yuv 4:4:4 multiples of 1 pixel multiples of 1 line 8 pixels/8 lines yuv 4:2:2 multiples of 2 pixels multiples of 1 line 16 pixels/8 lines yuv 4:2:0 multiples of 2 pixels multiples of 2 lines 16 pixels/16 lines yuv 4:1:1 multiples of 4 pixels multiples of 1 line 32 pixels/8 lines free datasheet http:///
page 204 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 10 reserved the default value for this bit is 0. bits 9-0 capture resizer start y position bits [9:0] these bits determine the y start position for the capture resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. bit 10 reserved the default value for this bit is 0. bits 9-0 capture resizer end x position bits [9:0] these bits determine the x end position for the capture resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. bit 10 reserved the default value for this bit is 0. bits 9-0 capture resizer end y position bits [9:0] these bits determine the y end position for the capture resizer. these bits must be pro- grammed according to the restrictions in section 17.3, ?resizer restrictions? on page 337. reg[0966h] capture resizer start y position register default = 0000h read/write n/a reserved capture resizer start y position bits 9-8 15 14 13 12 11 10 9 8 capture resizer start y position bits 7-0 76543210 reg[0968h] capture resizer end x position register default = 027fh read/write n/a reserved capture resizer end x position bits 9-8 15 14 13 12 11 10 9 8 capture resizer end x position bits 7-0 76543210 reg[096ah] capture resizer end y position register default = 01dfh read/write n/a reserved capture resizer end y position bits 9-8 15 14 13 12 11 10 9 8 capture resizer end y position bits 7-0 76543210 free datasheet http:///
epson research and development page 205 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 13-8 capture resizer vertical scaling rate bits [5:0] these bits determine the capture resizer vertical scaling rate when independent horizon- tal/vertical scaling is enabled (reg[0960h] bit 2 = 1). not all scaling rates are available for all scaling modes (see reg[096eh] bits 1-0). for a summary of the available scaling rate/mode options, see table 10-46: ?capture resizer vertical scaling rate selection,? on page 206. reg[096ch] capture resizer operation setting register 0 default = 0101h read/write n/a capture resizer vertical scaling rate bits 5-0 15 14 13 12 11 10 9 8 n/a capture resizer horizontal scaling rate bits 5-0 7 6543210 free datasheet http:///
page 206 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 10-46: capture resizer vertical scaling rate selection reg[096ch] bits 13-8 capture resizer vertical scaling rate reg[096eh] bits 1-0 = 00 reg[096eh] bits 1-0 = 01 reg[096eh] bits 1-0 = 10 reg[096eh] bits 1-0 = 11 00 0000b reserved reserved reserved reserved 00 0001b n/a 1/1 1/1 reserved 00 0010b n/a 1/2 1/2 reserved 00 0011b n/a 1/3 1/3 reserved 00 0100b n/a 1/4 1/4 reserved 00 0101b n/a 1/5 1/5 reserved 00 0110b n/a 1/6 1/6 reserved 00 0111b n/a 1/7 1/7 reserved 00 1000b n/a 1/8 1/8 reserved 00 1001b n/a 1/9 1/9 reserved 00 1010b n/a 1/10 1/10 reserved 00 1011b n/a 1/11 1/11 reserved 00 1100b n/a 1/12 1/12 reserved 00 1101b n/a 1/13 1/13 reserved 00 1110b n/a 1/14 1/14 reserved 00 1111b n/a 1/15 1/15 reserved 01 0000b n/a 1/16 1/16 reserved 01 0001b n/a 1/17 1/17 reserved 01 0010b n/a 1/18 1/18 reserved 01 0011b n/a 1/19 1/19 reserved 01 0100b n/a 1/20 1/20 reserved 01 0101b n/a 1/21 1/21 reserved 01 0110b n/a 1/22 1/22 reserved 01 0111b n/a 1/23 1/23 reserved 01 1000b n/a 1/24 1/24 reserved 01 1001b n/a 1/25 1/25 reserved 01 1010b n/a 1/26 1/26 reserved 01 1011b n/a 1/27 1/27 reserved 01 1100b n/a 1/28 1/28 reserved 01 1101b n/a 1/29 1/29 reserved 01 1110b n/a 1/30 1/30 reserved 01 1111b n/a 1/31 1/31 reserved 10 0000b n/a 1/32 1/32 reserved 10 0001b - 11 1111b reserved reserved reserved reserved free datasheet http:///
epson research and development page 207 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 5-0 capture resizer horizontal scaling rate bits [5:0] when independent horizontal/vertical scaling is disabled (reg[0960h] bit 2 = 0), these bits determine the vertical and horizontal scaling rate. when independent horizontal/verti- cal scaling is enabled (reg[0960h] bit 2 = 1), these bits only determine the horizontal scaling rate. not all scaling rates are available for all scaling modes (see reg[096eh] bits 1-0). for a summary of the available scaling rate/mode options, see table 10-47: ?capture resizer horizontal scaling rate selection,? on page 207. table 10-47: capture resizer horizontal scaling rate selection reg[096ch] bits 5-0 capture resizer horizontal scaling rate reg[096eh] bits 1-0 = 00 reg[096eh] bits 1-0 = 01 reg[096eh] bits 1-0 = 10 reg[096eh] bits 1-0 = 11 00 0000b reserved reserved reserved reserved 00 0001b n/a 1/1 1/1 reserved 00 0010b n/a 1/2 1/2 reserved 00 0011b n/a 1/3 reserved reserved 00 0100b n/a 1/4 1/4 reserved 00 0101b n/a 1/5 reserved reserved 00 0110b n/a 1/6 reserved reserved 00 0111b n/a 1/7 reserved reserved 00 1000b n/a 1/8 1/8 reserved 00 1001b n/a 1/9 reserved reserved 00 1010b n/a 1/10 reserved reserved 00 1011b n/a 1/11 reserved reserved 00 1100b n/a 1/12 reserved reserved 00 1101b n/a 1/13 reserved reserved 00 1110b n/a 1/14 reserved reserved 00 1111b n/a 1/15 reserved reserved 01 0000b n/a 1/16 1/16 reserved 01 0001b n/a 1/17 reserved reserved 01 0010b n/a 1/18 reserved reserved 01 0011b n/a 1/19 reserved reserved 01 0100b n/a 1/20 reserved reserved 01 0101b n/a 1/21 reserved reserved 01 0110b n/a 1/22 reserved reserved 01 0111b n/a 1/23 reserved reserved 01 1000b n/a 1/24 reserved reserved 01 1001b n/a 1/25 reserved reserved 01 1010b n/a 1/26 reserved reserved 01 1011b n/a 1/27 reserved reserved 01 1100b n/a 1/28 reserved reserved 01 1101b n/a 1/29 reserved reserved 01 1110b n/a 1/30 reserved reserved 01 1111b n/a 1/31 reserved reserved 10 0000b n/a 1/32 1/32 reserved 10 0001b - 11 1111b reserved reserved reserved reserved free datasheet http:///
page 208 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 3-2 reserved the default value for these bits is 0. bit 1-0 capture resizer scaling mode bits[1:0] these bits determine the capture resizer scaling mode. not all scaling rates are available for all scaling modes. before selecting a scaling mode, set the capture resizer vertical scaling rate bits (reg[096eh] bits 13-8) and/or the capture resizer horizontal scaling rate bits (reg[096ch] bits 5-0) to a valid scaling rate. enabling a scaling mode with an unsupported scaling rate (reserved or n/a) may turn off the capture resizer. reg[096eh] capture resizer operation setting register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved capture resizer scaling mode bits 1-0 7 6 5 43210 table 10-48: capture resizer scaling mode selection reg[096eh] bits 1-0 capture resizer scaling mode 00b no resizer scaling 01b v/h reduction 10b v: reduction, h: average 11b reserved free datasheet http:///
epson research and development page 209 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.14 jpeg module registers bits 15-12 reserved the default value for these bits is 0. bit 8 jpeg 180 rotation enable this bit is only for camera data encode. this bit selects the rotation mode for jpeg encoded data. for an overview diagram, see section 18.4, ?jpeg 180 rotate encode diagram? on page 344. when this bit = 0, the jpeg encoded data is normal. when this bit = 1, the jpeg encoded data is rotated 180. note the dimensions of the image must be in mcu size multiples. bit 7 jpeg module software reset (write only) this bit initiates a software reset of the internal jpeg module circuit. the jpeg module should be reset using this bit before each jpeg encode operation. this bit resets only the internal jpeg module circuit and has no effect on the jpeg codec registers (reg[1000h]-[17a2h], the jpeg codec or the jpeg module registers (reg[0980h]-[09e0h]), except as follows. reg[0984] is reset except for bits 14, 5, and 1. reg[09b4] is reset reg[09b6] is reset reg[09ac] is reset reg[09aa] is reset reg[09a8] is reset reg[09a2] is reset to reset the jpeg codec, set the jpeg codec software reset bit (reg[1002h] bit 7) to 1. when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the jpeg module is reset. bit 6 reserved the default value for this bit is 0. bit 5 reserved the default value for this bit is 0. reg[0980h] jpeg control register default = 0000h read/write reserved n/a jpeg 180 rotation enable 15 14 13 12 11 10 98 jpeg module sw reset (wo) reserved yuv data no offset select jpeg data control bits 2-0 jpeg module enable 76543210 free datasheet http:///
page 210 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 4 yuv data no offset select this bit specifies whether an offset is applied to the u and v data when in yuv capture, yuv display, host encode, and host decode modes, reg[0980h] bits [3:1] = 001b, 011b, 100b, 101b, or 111b. this bit is used in conjunction with reg[0110h] bit 8 to select the desired yuv output capture range for yuv capture mode. when this bit = 0, an offset is applied to the u and v data (msb is inverted). when this bit = 1, no offset is applied to the u and v data is not modified. the yuv data range depends on the interface data range and the yuv data no offset select bit. for host decode mode, this bit must be set to 1. table 10-49: yuv output range selection (reg[0980h] bits 3-1 = 011b or 111b) camera interface input yuv data reg[0110h] bit 8 reg[0980h] bit 4 yuv output data range straight data 0 0 0 =< y =< 255 -128 =< u =< 127 -128 =< v =< 127 or 16 =< y =< 235 -112 =< cb=< 112 -112 =< cr=< 112 1 0 =< y =< 255 0 =< u =< 255 0 =< v =< 255 or 16 =< y =< 235 16 =< cb=< 240 16 =< cr =< 240 1 0 0 =< y =< 255 0 =< u =< 255 0 =< v =< 255 or 16 =< y =< 235 16 =< cb =< 240 16 =< cr =< 240 1 0 =< y =< 255 -128 =< u =< 127 -128 =< v =< 127 or 16 =< y =< 235 -112 =< cb =< 112 -112 =< cr =< 112 free datasheet http:///
epson research and development page 211 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential offset data 0 0 0 =< y =< 255 0 =< u =< 255 0 =< v =< 255 or 16 =< y =< 235 16 =< cb =< 240 16 =< cr =< 240 1 0 =< y =< 255 -128 =< u =< 127 -128 =< v =< 127 or 16 =< y =< 235 -112 =< cb =< 112 -112 =< cr =< 112 1 0 0 =< y =< 255 -128 =< u =< 127 -128 =< v =< 127 or 16 =< y =< 235 -112 =< cb=< 112 -112 =< cr=< 112 1 0 =< y =< 255 0 =< u =< 255 0 =< v =< 255 or 16 =< y =< 235 16 =< cb=< 240 16 =< cr =< 240 table 10-49: yuv output range selection (reg[0980h] bits 3-1 = 011b or 111b) (continued) camera interface input yuv data reg[0110h] bit 8 reg[0980h] bit 4 yuv output data range free datasheet http:///
page 212 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 10-50: yuv input range selection (reg[0980h] bits 3-1 = 001b, 100b or 101b) host interface input yuv data reg[0980h] bit 4 yuv input data range straight data 0 0 y 255 -128 u 127 -128 v 127 or 16 y 235 -112 cb 112 -112 cr 112 1 0 y 255 0 u 255 0 v 255 or 16 y 235 16 cb 240 16 cr 240 offset data 0 0 y 255 0 u 255 0 v 255 or 16 y 235 16 cb 240 16 cr 240 1 0 y 255 -128 u 127 -128 v 127 or 16 y 235 -112 cb 112 -112 cr 112 free datasheet http:///
epson research and development page 213 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 3-1 jpeg data control bits [2:0] bit 0 jpeg module enable this bit enables/disables the jpeg module and its associated registers. if the jpeg mod- ule is disabled, reg[1000h] - reg[17a2h] must not be accessed. when this bit = 0, the jpeg module is disabled and the clock source is disabled. when this bit = 1, the jpeg module is enabled and a clock source is supplied. note the jpeg module must be disabled before the view resizer enable bit (reg[0940h] bit 0) or the capture resizer enable bit (reg[0960h] bit 0) are disabled. table 10-51: jpeg data mode selection reg[0980h] bits 3-1 jpeg data mode description 000b jpeg encode/decode in this mode the encode data paths are: ? camera interface => capture resizer => jpeg line buffer => codec core => jpeg fifo => host interface ? display buffer => capture resizer => jpeg line buffer => codec core => jpeg fifo => host interface ? host interface => capture resizer => jpeg line buffer => codec core => jpeg fifo => host interface in this mode the decode data path is: ? host interface => jpeg fifo => codec core => jpeg line buffer => view resizer => display buffer 001b yuv data input from host (yuv 4:2:2) the data by-passes the jpeg module. 010b reserved 011b yuv data output to host (yuv 4:2:2) the data by-passes the jpeg module. 100b host input/output jpeg encode/decode (yuv 4:2:0 or yuv 4:2:2) in this mode the encode data path is: ? host interface => jpeg line buffer => capture resizer => codec core => jpeg fifo => host interface in this mode the decode data path is: ? host interface => jpeg fifo => codec core => jpeg line buffer => view resizer => host interface 101b yuv data input from host (yuv 4:2:0) the data by-passes the jpeg module. 110b reserved 111b yuv data output to host (yuv 4:2:0) the data by-passes the jpeg module. free datasheet http:///
page 214 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 15 reserved the default value for this bit is 1. bit 14 jpeg codec file out status (read only) this bit indicates the status of the jpeg codec output. when this bit = 0, the jpeg codec is not outputing encoded data. when this bit = 1, the jpeg codec is encoding or outputing encoded data. bits 13-12 jpeg fifo threshold status bits [1:0] (read only) these bits indicate how much data is currently in the jpeg fifo. see the jpeg fifo size register (reg[09a4h]) for information on setting the jpeg fifo size. reg[0982h] jpeg status flag register default = 8080h read/write reserved jpeg codec file out status (ro) jpeg fifo threshold status bits 1-0 (ro) encode size limit violation flag jpeg fifo threshold trigger flag jpeg fifo full flag jpeg fifo empty flag 15 14 13 12 11 10 9 8 reserved jpeg decode complete flag decode marker read flag reserved jpeg line buffer overflow flag (ro) jpeg codec interrupt flag (ro) jpeg line buffer interrupt flag (ro) 76543 2 10 table 10-52: jpeg fifo threshold status reg[0982h] bits 13-12 jpeg fifo threshold status 00b no data (same as empty 01b more than 4 bytes of data exist 10b more than 1/4 of specified fifo size data exists 11b more than 1/2 of specified fifo size data exists free datasheet http:///
epson research and development page 215 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 11 encode size limit violation flag this flag is asserted when the jpeg compressed data size is over the encode size limit as specified in the encode size limit registers (reg[09b0h], reg[09b2h]). this flag is masked by the jpeg encode size limit violation interrupt enable bit and is only avail- able when reg[0986h] bit 11 = 1. for reads: when this bit = 0, no violation has occurred. when this bit = 1, an encode size limit violation has occurred. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the encode size limit violation flag is cleared. note the encode size limit violation flag can only be cleared when an encode size limit violation no longer exists. this can be done by setting the encode size limit to a value greater then the encode size result (reg[09b0h] - reg[09b2h] > reg[09b4h] - reg[09b6h]), or by resetting the jpeg module (reg[0980h] bit 7 = 1). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 10 jpeg fifo threshold trigger flag this flag is asserted when the amount of data in the jpeg fifo meets the condition spec- ified by the jpeg fifo trigger threshold bits (reg[09a0h] bits 5-4). this flag is masked by the jpeg fifo threshold trigger interrupt enable bit and is only available when reg[0986h] bit 10 = 1. for reads: when this bit = 0, the amount of data in the jpeg fifo is less than the jpeg fifo trig- ger threshold. when this bit = 1, the amount of data in the jpeg fifo has reached the jpeg fifo trig- ger threshold. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the fifo threshold trigger flag is cleared. note the jpeg fifo threshold trigger flag can only be cleared when a jpeg fifo thresh- old trigger flag condition no longer exists. this can be done by increasing the jpeg fifo threshold (reg[09a0h] bits 5-4), emptying the jpeg fifo until it drops below the specified threshold, or by resetting the jpeg module (reg[0980h] bit 7 = 1). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. free datasheet http:///
page 216 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 9 jpeg fifo full flag this flag is asserted when the jpeg fifo is full. this flag is masked by the jpeg fifo full interrupt enable bit and is only available when reg[0986h] bit 9 = 1. for reads: when this bit = 0, the jpeg fifo is not full. when this bit = 1, the jpeg fifo is full. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the jpeg fifo full flag is cleared. note the jpeg fifo full flag can only be cleared when the jpeg fifo is no longer full, or after a jpeg module software reset (reg[0980h] bit 7 = 1). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 8 jpeg fifo empty flag this flag is asserted when the jpeg fifo is empty. this flag is masked by the jpeg fifo empty interrupt enable bit and is only available when reg[0986h] bit 8 = 1. for reads: when this bit = 0, the jpeg fifo is not empty. when this bit = 1, the jpeg fifo is empty. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the jpeg fifo empty flag is cleared. note the jpeg fifo empty flag can only be cleared when the jpeg fifo is no longer emp- ty, or after a jpeg module software reset (reg[0980h] bit 7 = 1). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 7 reserved the default value for this bit is 1. bit 6 reserved the default value for this bit is 0. free datasheet http:///
epson research and development page 217 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 5 jpeg decode complete flag this flag is asserted when the jpeg decode operation is finished. this flag is masked by the jpeg decode complete interrupt enable bit and is only available when reg[0986h] bit 5 = 1. for reads: when this bit = 0, the jpeg decode operation is not finished yet. when this bit = 1, the jpeg decode operation is finished. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, this bit is cleared. note when error detection is enabled (reg[101ch] bits 1-0 = 01b) and an error is detected while decoding a jpeg image, this status bit is not set at the end of the decode process. note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 4 decode marker read flag this flag is asserted during the jpeg decoding process when decoded marker information is read from the jpeg file. this flag is masked by the jpeg decode marker read inter- rupt enable bit and is only available when reg[0986h] bit 4 = 1. when this bit = 0, a jpeg decode marker has not been read. when this bit = 1, a jpeg decode marker has been read. to clear this flag, disable the decode marker read interrupt enable bit (reg[0986h] bit 4 = 0). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 3 reserved the default value for this bit is 0. bit 2 jpeg line buffer overflow flag (read only) this flag is asserted when a jpeg line buffer overflow occurs. this flag is masked by the jpeg line buffer overflow interrupt enable bit and is only available when reg[0986h] bit 2 = 1. when this bit = 0, a jpeg line buffer overflow has not occurred. when this bit = 1, a jpeg line buffer overflow has occurred. to clear this flag, perform a jpeg software reset (reg[0980h] bit 7 = 1). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. free datasheet http:///
page 218 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 1 jpeg codec interrupt flag (read only) this flag is asserted when the jpeg codec generates an interrupt. this flag is masked by the jpeg codec interrupt enable bit and is only available when reg[0986h] bit 1 = 1). when this bit = 0, the jpeg codec has not generated an interrupt. when this bit = 1, the jpeg codec has generated an interrupt. to clear this flag, read the jpeg operation status bit (reg[1004h] bit 0). note for further information on the use of this bit, see section 19.1.2, ?jpeg codec inter- rupts? on page 347. bit 0 jpeg line buffer interrupt flag (read only) this bit is valid only when yuv capture/display or host decode/encode mode is selected (reg[0980h] bits 3-1 000b). this bit is set when a jpeg line buffer interrupt occurs in reg[09c0h] and is used for yuv data transfers or host decode/encode opera- tions with interrupt handling. this flag is masked by the jpeg line buffer interrupt enable bit and is only available when reg[0986h] bit 0 = 1). this bit is cleared when all jpeg line buffer interrupt requests are cleared in reg[09c0h]. when this bit = 0, the jpeg line buffer has not generated an interrupt. when this bit = 1, the jpeg line buffer has generated an interrupt. bit 15 reserved the default value for this bit is 1. bit 14 jpeg codec file out status (read only) this bit provides the status of the jpeg codec output. when this bit = 0, the jpeg codec is not outputing encoded data. when this bit = 1, the jpeg codec is encoding or outputing encoded data. note this bit has the same functionality as reg[0982h] bit 14. reg[0984h] jpeg raw status flag register default = 8180h read only reserved jpeg codec file out status jpeg fifo threshold status bits 1-0 raw encode size limit violation flag raw jpeg fifo threshold trigger flag raw jpeg fifo full flag raw jpeg fifo empty flag 15 14 13 12 11 10 9 8 reserved raw jpeg decode complete flag raw jpeg decode marker read flag reserved raw jpeg line buffer overflow flag raw jpeg codec interrupt flag raw jpeg line buffer interrupt flag 76543 2 10 free datasheet http:///
epson research and development page 219 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 13-12 jpeg fifo threshold status bits [1:0] (read only) these bits indicate how much data is currently in the jpeg fifo. see the jpeg fifo size register (reg[09a4h) for information on setting the jpeg fifo size. note these bits have the same functionality as reg[0982h] bits 13-12. bit 11 raw encode size limit violation flag (read only) this flag is asserted when the jpeg encoded data size is over the size limit as specified in the encode size limit registers (reg[09b02h] - reg[09b2h]). this flag is not affected by the jpeg encode size limit violation interrupt enable bit (reg[0986h] bit 11). when this bit = 0, no violation has occurred. when this bit = 1, an encode size limit violation has occurred. to clear this flag, write a 1 to the encode size limit violation flag, reg[0982h] bit 11, when an encode size limit violation condition no longer exists. (i.e. set the encode size limit, reg[09b0h] and reg[09b2h] > encode size result, reg[09b4h] and reg[09b6h], or reset the jpeg module, reg[0980h] bit 7 = 1.) bit 10 raw jpeg fifo threshold trigger flag (read only) this flag is asserted when the amount of data in the jpeg fifo meets the condition spec- ified by the jpeg fifo trigger threshold bits (reg[09a0] bits 5-4). this flag is not affected by the jpeg fifo threshold trigger interrupt enable bit (reg[0986h] bit 10). when this bit = 0, the amount of data in the jpeg fifo is less than the jpeg fifo trig- ger threshold. when this bit = 1, the amount of data in the jpeg fifo has reached the jpeg fifo trig- ger threshold. to clear this flag, write a 1 to the jpeg fifo threshold trigger flag, reg[0982] bit 10, when a jpeg fifo threshold trigger condition no longer exists. (i.e. set the jpeg fifo threshold in reg[09a0] bits [5:4] greater, empty the jpeg fifo until it?s level is below the specified threshold, or reset the jpeg module, reg[0980] bit 7 = 1.) bit 9 raw jpeg fifo full flag (read only) this flag is asserted when the jpeg fifo is full. this flag is not affected by the jpeg fifo full interrupt enable bit (reg[0986h] bit 9). when this bit = 0, the jpeg fifo is not full. when this bit = 1, the jpeg fifo is full. to clear this flag, write a 1 to the jpeg fifo full flag, reg[0982h] bit 9, when the jpeg fifo is no longer full or after a jpeg module reset, reg[0980h] bit 7 = 1. table 10-53: jpeg fifo threshold status reg[0984h] bits 13-12 jpeg fifo threshold status 00b no data (same as empty 01b more than 4 bytes of data exist 10b more than 1/4 of specified fifo size data exists 11b more than 1/2 of specified fifo size data exists free datasheet http:///
page 220 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 8 raw jpeg fifo empty flag (read only) this flag is asserted when the jpeg fifo is empty. this flag is not affected by the jpeg fifo empty interrupt enable bit (reg[0986h] bit 8). when this bit = 0, the jpeg fifo is not empty. when this bit = 1, the jpeg fifo is empty. to clear this flag, write a 1 to the jpeg fifo empty flag, reg[0982h] bit 8, when the jpeg fifo is no longer empty or after a jpeg module reset, reg[0980h] bit 7 = 1. note this bit is not affected by the jpeg fifo clear bit (reg[09a0h] bit 2). bit 7 reserved the default value for this bit is 1. bit 6 reserved the default value for this bit is 0. bit 5 raw jpeg decode complete flag (read only) this flag is asserted when the jpeg decode operation is finished. this flag is not affected by the jpeg decode complete interrupt enable bit (reg[0986h] bit 5). when this bit = 0, the jpeg decode operation is not finished yet. when this bit = 1, the jpeg decode operation is finished. to clear this flag, write a 1 to the jpeg decode complete flag (reg[0982h] bit 5 = 1). note when error detection is enabled (reg[101ch] bits 1-0 = 01) and an error is detected while decoding a jpeg image, this status bit is not set at the end of the decode process. bit 4 raw jpeg decode marker read flag (read only) this flag is asserted during the jpeg decoding process when decoded marker information is read from the jpeg file and when reg[0986h] bit 4 = 1. when this bit = 0, a jpeg decode marker has not been read. when this bit = 1, a jpeg decode marker has been read. to clear this flag, disable the jpeg decode marker read interrupt enable bit (reg[0986h] bit 4 = 0). bit 3 reserved the default value for this bit is 0. bit 2 raw jpeg line buffer overflow flag (read only) this flag is asserted when a jpeg line buffer overflow occurs. this flag is not affected by the jpeg line buffer overflow interrupt enable (reg[0986h] bit 2). when this bit = 0, a jpeg line buffer overflow has not occurred. when this bit = 1, a jpeg line buffer overflow has occurred. to clear this flag, perform a jpeg module software reset (reg[0980h] bit 7 = 1). free datasheet http:///
epson research and development page 221 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 1 raw jpeg codec interrupt flag (read only) this flag is asserted when an interrupt is generated by the jpeg codec. this flag is not affected by the jpeg codec interrupt enable bit (reg[0986h] bit 1). when this bit = 0, no interrupt has been generated. when this bit = 1, the jpeg codec has generated an interrupt. to clear this flag, read the jpeg operation status bit (reg[1004h] bit 0). bit 0 raw jpeg line buffer interrupt flag this bit is valid only when yuv capture/display mode is selected (reg[0980h] bits 3-1 000). this flag is not affected by the jpeg line buffer interrupt enable bit (reg[0986h] bit 0). this bit is set when a jpeg line buffer interrupt occurs in reg[09c0h] and is cleared when all jpeg line buffer interrupt requests are cleared in reg[09c0h]. when this bit = 0, the jpeg line buffer has not generated an interrupt. when this bit = 1, the jpeg line buffer has generated an interrupt. bits 15-12 reserved the default value for these bits is 0. bit 11 encode size limit violation interrupt enable this bit controls the encode size limit violation interrupt. the status of this interrupt can be determined using the encode size limit violation flag bit (reg[0982h] bit 11). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 10 jpeg fifo threshold trigger interrupt enable this bit controls the jpeg fifo threshold trigger interrupt. the status of this interrupt can be determined using the jpeg fifo threshold trigger flag bit (reg[0982h] bit 10). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 9 jpeg fifo full interrupt enable this bit controls the jpeg fifo full interrupt. the status of this interrupt can be deter- mined using the jpeg fifo full flag bit (reg[0982h] bit 9). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. reg[0986h] jpeg interrupt control register default = 0000h read/write reserved encode size limit violation interrupt enable jpeg fifo threshold trigger interrupt enable jpeg fifo full interrupt enable jpeg fifo empty interrupt enable 15 14 13 12 11 10 9 8 reserved jpeg decode complete interrupt enable decode marker read interrupt enable reserved jpeg line buffer overflow interrupt enable jpeg codec interrupt enable jpeg line buffer interrupt enable 76543210 free datasheet http:///
page 222 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 8 jpeg fifo empty interrupt enable this bit controls the jpeg fifo empty interrupt. the status of this interrupt can be deter- mined using the jpeg fifo empty flag bit (reg[0982h] bit 8). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 7 reserved the default value for this bit is 0. bit 6 reserved the default value for this bit is 0. bit 5 jpeg decode complete interrupt enable this bit controls the jpeg decode complete interrupt. the status of this interrupt can be determined using the jpeg decode complete flag bit (reg[0982h] bit 5). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 4 jpeg decode marker read interrupt enable this bit controls the jpeg decode marker read interrupt. the status of this interrupt can be determined using the jpeg decode complete flag (reg[0982h] bit 4). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 3 reserved the default value for this bit is 0. bit 2 jpeg line buffer overflow interrupt enable this bit controls the jpeg line buffer overflow interrupt. the status of this interrupt can be determined using the line buffer overflow flag (reg[0982h] bit 2). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 1 jpeg codec interrupt enable this bit controls the jpeg codec interrupt. the status of this interrupt can be determined using the jpeg codec interrupt flag (reg[0982h] bit 1). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 0 jpeg line buffer interrupt enable this bit controls the jpeg line buffer interrupt. the status of this interrupt can be deter- mined using the jpeg line buffer interrupt flag (reg[0982h] bit 0). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. this bit should be disabled if yuv data in not being input from host and then displayed (reg[0980h] bits 3-1 = 001b or 101b). reg[0988h] is reserved this register is reserved and should not be written. free datasheet http:///
epson research and development page 223 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 jpeg start/stop control (write only) this bit controls the jpeg codec for both jpeg encode mode and yuv data capture (jpeg bypass) mode. this bit is not used for jpeg decoding. for jpeg encode: when this bit is set to 0, the jpeg codec will be ready to capture from the next frame. when this bit is set to 1, the jpeg codec starts capturing the next frame and then stops. for yuv data capture (jpeg bypass): when this bit is set to 0, yuv data capturing stops at the end of the current frame. when this bit is set to 1, yuv data capturing starts from the next frame. reg[098ch] through reg[098eh] are reserved these registers are reserved and should not be written. reg[098ah] jpeg code start/stop control register default = 0000h write only n/a 15 14 13 12 11 10 9 8 n/a jpeg start/stop control 7 6 5 4 3 2 10 free datasheet http:///
page 224 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.15 jpeg fifo setting register bits 15-6 reserved the default value for these bits is 0. bits 5-4 jpeg fifo trigger threshold bits[1:0] these bits set the jpeg fifo threshold trigger flag (reg[0982h] bit 10) when the spec- ified conditions are met. . bit 3 reserved the default value for this bit is 0. reg[09a0h] jpeg fifo control register default = 0000h read/write reserved 15 14 13 12 11 10 9 8 reserved jpeg fifo trigger threshold bits 1-0 reserved jpeg fifo clear (wo) jpeg fifo direction (ro) n/a 7654321 0 table 10-54: jpeg fifo trigger threshold selection reg[09a0h] bits 5-4 jpeg fifo trigger threshold 00b never trigger 01b trigger when the jpeg fifo contains 4 bytes of data or more 10b trigger when the jpeg fifo contains more than 1/4 of the specified jpeg fifo size (reg[09a4h] bits 3-0) 11b trigger when the jpeg fifo contains more than 1/2 of the specified jpeg fifo size (reg[09a4h] bits 3-0) free datasheet http:///
epson research and development page 225 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 2 jpeg fifo clear (write only) this bit clears the jpeg fifo. it is recommended that the jpeg module should also be reset (reg[0980h] bit 7 = 1) when the jpeg fifo is cleared. when this bit = 0, there is no hardware effect. when this bit = 1, the jpeg fifo, the jpeg fifo read/write pointer registers (reg[09aah]-[09ach]), and the jpeg fifo valid data size registers (reg[09a8h] are cleared. the following sequence is used clear the jpeg fifo. 1. clear the jpeg fifo, reg[09a0h] bit 2 = 1. 2. reset the jpeg module, reg[0980h] bit 7 = 1. 3. perform 2 dummy reads from reg[09a6h] to ensure that the jpeg fifo is empty. note clearing the jpeg fifo using this bit has no effect on the raw jpeg fifo empty flag (reg[0984h] bit 8). note this bit only clears the jpeg fifo and does not clear the jpeg line buffer. for details on using the jpeg fifo, see section 19.1.1, ?jpeg fifo? on page 346. bit 1 jpeg fifo direction bit (read only) this bit indicates the configuration of the jpeg fifo. when this bit = 0, the jpeg fifo is configured to receive (encode process). when this bit = 1, the jpeg fifo is configured to transmit (decode process). bit 15 reserved the default value for this bit is 0. reg[09a2h] jpeg fifo status register default = 8001h read only reserved n/a 15 14 13 12 11 10 9 8 reserved jpeg fifo threshold status bits 1-0 jpeg fifo full status jpeg fifo empty status 76543210 free datasheet http:///
page 226 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 3-2 jpeg fifo threshold status bits [1:0] (read only) these bits indicate how much data is currently in the jpeg fifo. see the jpeg fifo size register (reg[09a4h]) for information on setting the jpeg fifo size. note these bits have the same functionality as reg[0982h] bits 13-12. bit 1 jpeg fifo full status (read only) this bit indicates whether the jpeg fifo is full. when this bit = 0, the jpeg fifo is not full. when this bit = 1, the jpeg fifo is full. bit 0 jpeg fifo empty status (read only) this bit indicates that the jpeg fifo is empty. when this bit = 0, the jpeg fifo is not empty. when this bit = 1, the jpeg fifo is empty. bits 15-5 reserved the default value for these bits is 0. bits 4-0 jpeg fifo size bits [4:0] these bits determine the jpeg fifo size in 4k byte units. the maximum size of the jpeg fifo is 128k bytes. these bits also specify the amount of memory reserved for the jpeg fifo. jpeg fifo size = (reg[09a4h] bits 4-0 + 1) x 4k bytes note for further information on S1D13717 memory mapping, see section 8, ?memory allo- cation? on page 106. table 10-55: jpeg fifo threshold status reg[09a2h] bits 3-2 jpeg fifo threshold status 00b no data (same as empty 01b more than 4 bytes of data exist 10b more than 1/4 of specified fifo size data exists 11b more than 1/2 of specified fifo size data exists reg[09a4h] jpeg fifo size register default = 0000h read/write reserved 15 14 13 12 11 10 9 8 reserved jpeg fifo size bits 4-0 76543210 free datasheet http:///
epson research and development page 227 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 15-0 jpeg fifo read/write port bits[15:0] these bits are the access port for the jpeg fifo. the current address pointed to by the port can be determined using the jpeg fifo read pointer register (reg[09aah) and the jpeg fifo write pointer register (reg[09ach]). when jpeg encoding is selected, these bits are used as the jpeg fifo read data port. when jpeg decoding is selected, these bits are used as the jpeg fifo write data port. when yuv data is output to the host interface (reg[0980] bits 3-1 = 011b or 111b), these bits are used as the jpeg fifo read data port. note since the jpeg fifo is 32 bits wide and the host cpu interface is 16 bits wide, this register must be accessed an even number of times. bits 15-0 jpeg fifo valid data size bits[15:0] (read only) these bits indicate the valid data size in 32-bit units which can be read from the jpeg fifo. if the jpeg file size is not aligned on 32-bit boundaries, the jpeg fifo may con- tain more data (1 to 3 bytes) than the indicated size. see the encode size result registers (reg[09b4h]-[09b6h]) to determine the correct data size. bits 15-0 jpeg fifo read pointer bits[15:0] (read only) these bits are used during evaluation and are for reference only. these bits indicate the 32-bit read pointer into the jpeg fifo. the read pointer is automatically incremented when either a read or write to/from the jpeg fifo read/write port register (reg[09a6h]) takes place. for details on the jpeg fifo, see section 19.1.1, ?jpeg fifo? on page 346. reg[09a6h] jpeg fifo read/write port register default = not applicable read/write jpeg fifo read/write port bits 15-8 15 14 13 12 11 10 9 8 jpeg fifo read/write port bits 7-0 76543210 reg[09a8h] jpeg fifo valid data size register default = 0000h read only jpeg fifo valid data size bits 15-8 15 14 13 12 11 10 9 8 jpeg fifo valid data size bits 7-0 76543210 reg[09aah] jpeg fifo read pointer register default = 0000h read only jpeg fifo read pointer bits 15-8 15 14 13 12 11 10 9 8 jpeg fifo read pointer bits 7-0 76543210 free datasheet http:///
page 228 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 15-0 jpeg fifo write pointer bits[15:0] (read only) these bits are used during evaluation and are for reference only. these bits indicate the 32-bit write pointer into the jpeg fifo. the write pointer is automatically incremented when a write to the jpeg fifo read/write port register (reg[09a6h]) takes place. for details on the jpeg fifo, see section 19.1.1, ?jpeg fifo? on page 346. reg[09b2h] bits 7-0 reg[09b0h] bits 15-0 encode size limit bits[23:0] these bits are required for the jpeg encode process only. these bits specify the data size limit, in bytes, for the encoded jpeg file. note setting these registers to 0 will disable the encode size limit violation function and reg[0984h] bit 11 will not be set. reg[09ach] jpeg fifo write pointer register default = 0000h read only jpeg fifo write pointer bits 15-8 15 14 13 12 11 10 9 8 jpeg fifo write pointer bits 7-0 76543210 reg[09b0h] encode size limit register 0 default = 0000h read/write encode size limit bits 15-8 15 14 13 12 11 10 9 8 encode size limit bits 7-0 76543210 reg[09b2h] encode size limit register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 encode size limit bits 23-16 76543210 free datasheet http:///
epson research and development page 229 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[09b6h] bits 7-0 reg[09b4h] bits 15-0 encode size result bits[23:0] (read only) these bits are required for the jpeg encode process only. these bits indicate the data size result, in bytes, for the encoded jpeg file. reg[09bah] bits 7-0 reg[09b8h] bits 15-0 jpeg file size bits[23:0] these bits are required for the jpeg decode process only. these bits specify the jpeg file size in bytes and must be set before the host begins writing decoded data to the jpeg fifo. reg[09bch] is reserved this register is reserved and should not be written. reg[09b4h] encode size result register 0 default = 0000h read only encode size result bits 15-8 15 14 13 12 11 10 9 8 encode size result bits 7-0 76543210 reg[09b6h] encode size result register 1 default = 0000h read only n/a 15 14 13 12 11 10 9 8 encode size result bits 23-16 76543210 reg[09b8h] jpeg file size register 0 default = 0000h read/write jpeg file size bits 15-8 15 14 13 12 11 10 9 8 jpeg file size bits 7-0 76543210 reg[09bah] jpeg file size register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 jpeg file size bits 23-16 76543210 free datasheet http:///
page 230 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.16 jpeg line buffer setting register bit 2 jpeg line buffer full flag this flag is asserted when the jpeg line buffer becomes full. this flag is masked by the jpeg line buffer full interrupt enable bit and is only available when reg[09c6h] bit 2 = 1. this bit is only valid for yuv capture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). when this bit = 0, the jpeg line buffer is not full. when this bit = 1, the jpeg line buffer is full. to clear this flag, when the jpeg line buffer is not full, write a 1 to this bit. bit 1 jpeg line buffer half full flag this flag is asserted when the jpeg line buffer has become half full. this flag is masked by the jpeg line buffer half full interrupt enable bit and is only available when reg[09c6h] bit 1 = 1. this bit is only valid for yuv capture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). when this bit = 0, the jpeg line buffer is not half full. when this bit = 1, the jpeg line buffer is half full. to clear this flag, when the jpeg line buffer is not half full, write a 1 to this bit. bit 0 jpeg line buffer empty flag this flag is asserted when the jpeg line buffer contains less than or equal to 16 bytes of yuv 4:2:2 data or 8 bytes of yuv 4:2:0 data. this flag is masked by the jpeg line buffer empty interrupt enable bit and is only available when reg[09c6h] bit 0 = 1. this bit is only valid for yuv capture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). when this bit = 0, the jpeg line buffer is not empty. when this bit = 1, the jpeg line buffer contains 16 bytes or less of yuv 4:2:2 data or 8 bytes or less of yuv 4:2:0 data. to clear this flag, when the jpeg line buffer is not empty, write a 1 to this bit. reg[09c0h] jpeg line buffer status flag register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a jpeg line buffer full flag jpeg line buffer half flag jpeg line buffer empty flag 7 6 5 4 3210 free datasheet http:///
epson research and development page 231 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 2 raw jpeg line buffer full flag (read only) this flag is asserted when the jpeg line buffer becomes full. this flag is not affected by the jpeg line buffer full interrupt enable bit (reg[09c6h] bit 2). this bit is only valid for yuv capture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). when this bit = 0, the jpeg line buffer is not full. when this bit = 1, the jpeg line buffer is full. to clear this flag, when the jpeg line buffer is not full, write a 1 to reg[09c0h] bit 2. bit 1 raw jpeg line buffer half full flag (read only) this flag is asserted when the jpeg line buffer becomes half full. this flag is not affected by the jpeg line buffer half full interrupt enable bit (reg[09c6h] bit 1). when this bit = 0, the jpeg line buffer is not half full. when this bit = 1, the jpeg line buffer is half full. this bit is only valid for yuv cap- ture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). to clear this flag, when the jpeg line buffer is not half full, write a 1 to reg[09c0h] bit 1. bit 0 raw jpeg line buffer empty flag (read only) this flag is asserted when the jpeg line buffer contains less than or equal to 16 bytes of yuv 4:2:2 data or 8 bytes of yuv 4:2:0 data. this flag is not affected by the jpeg line buffer empty interrupt enable bit (reg[09c6h] bit 0). this bit is only valid for yuv capture/display and host encode/decode modes (reg[0980h] bits 3-1 000b). when this bit = 0, the jpeg line buffer is not empty. when this bit = 1, the jpeg line buffer contains 16 bytes or less of yuv 4:2:2 data or 8 bytes or less of yuv 4:2:0 data. to clear this flag, when the jpeg line buffer is not empty, write a 1 to reg[09c0h] bit 0. reg[09c2h] jpeg line buffer raw status flag register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a raw jpeg line buffer full flag raw jpeg line buffer half flag raw jpeg line buffer empty flag 7 6 5 4 3210 free datasheet http:///
page 232 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 15-7 reserved the default value for bits 15 - 12 is 1 and the default value for bits 11 - 8 is 0. bit 2 raw jpeg line buffer full current status (read only) this flag indicates the current status of the jpeg line buffer. this flag is not affected by the jpeg line buffer full interrupt enable bit (reg[09c6h] bit 2). when this bit = 0, the jpeg line buffer is not full. when this bit = 1, the jpeg line buffer is full. bit 1 raw jpeg line buffer half full current status (read only) this flag indicates the current status of the jpeg line buffer. this flag is not affected by the jpeg line buffer half full interrupt enable bit (reg[09c6h] bit 1). when this bit = 0, the jpeg line buffer is not half full. when this bit = 1, the jpeg line buffer is half full. bit 0 raw line buffer empty current status (read only) this flag indicates the current status of the jpeg line buffer. this flag is not affected by the jpeg line buffer empty interrupt enable bit (reg[09c6h] bit 0). when this bit = 0, the jpeg line buffer is not empty. when this bit = 1, the jpeg line buffer contains 16 bytes or less of yuv 4:2:2 data or 8 bytes or less of yuv 4:2:0 data. bit 2 jpeg line buffer full interrupt enable this bit controls the jpeg line buffer full interrupt. the status of the interrupt can be determined using the jpeg line buffer full flag (reg[09c0h] bit 2). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 1 jpeg line buffer half full interrupt enable this bit controls the jpeg line buffer half full interrupt. the status of the interrupt can be determined using the jpeg line buffer half full flag (reg[09c0h] bit 1). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. reg[09c4h] jpeg line buffer raw current status register default = f001h read only reserved reserved reserved reserved reserved reserved reserved reserved 15 14 13 12 11 10 9 8 reserved n/a raw jpeg line buffer full current status raw jpeg line buffer half full current status raw jpeg line buffer empty current status 7 6 5 4 3210 reg[09c6h] jpeg line buffer interrupt control register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a jpeg line buffer full interrupt enable jpeg line buffer half full interrupt enable jpeg line buffer empty interrupt enable 7 6 5 4 3210 free datasheet http:///
epson research and development page 233 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 0 jpeg line buffer empty interrupt enable this bit controls the jpeg line buffer empty interrupt. the status of the interrupt can be determined using the jpeg line buffer empty flag (reg[09c0h] bit 0). when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. reg[09c8h] through reg[09ceh] are reserved these registers are reserved and should not be written. bit 15 reserved the default value for this bit is 0. bits 14-4 jpeg line buffer raw horizontal pixel size bits [10:0] (read only these bits provide actual number of the horizontal pixel size supported by the jpeg line buffer as set in reg[09d0h] bits 2-0. bit 3 reserved the default value for this bit is 0. bits 2-0 jpeg line buffer horizontal pixel size bits [2:0] these bits indicate the horizontal pixel size supported by the jpeg line buffer. bits 15-7 reserved the default value for these bits is 0. reg[09d0h] jpeg line buffer configuration register default = 2800h read/write reserved jpeg line buffer raw horizontal pixel size bits 10-4 (ro) 15 14 13 12 11 10 9 8 jpeg line buffer raw horizontal pixel size bits 3-0 (ro) reserved jpeg line buffer horizontal pixel size bits 2-0 76543210 table 10-56: supported horizontal pixel size reg[09d0h] bits 2-0 supported horizontal pixel size line buffer size 000b vga (640) 30k bytes 001b svga (800) 38k bytes 010b xga (1024) 48k bytes 011b - 111b reserved reg[09d2h] jpeg line buffer address offset register default = 0040h read/write reserved 15 14 13 12 11 10 9 8 reserved jpeg line buffer address offset bits 6-0 76543210 free datasheet http:///
page 234 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 6-0 jpeg line buffer address offset bits [6:0] these bits provide the address offset of the jpeg line buffer, and therefore the size (default is 256 bytes), as follows. reg[09d2h] bits 6-0 = [(96 x 1024) - (xsize x 2 x 24 x f)] / 1024 offset value (h) = (reg[09c2h] bits 6-0) x 400h + 20000h where: xsize = horizontal size = 640 f (yuv format) = 1 (4:2:0 & 4:4:4) | 0.75 (4:2:2) | 0.5 (4:1:1) >> 10 represents a 10 bit, shift right operator << 10 represents a 10 bit, shift left operator note yuv 4:4:4 format is possible for jpeg decoding only. reg[09d4h] through reg[09deh] are reserved these registers are reserved and should not be written. bits 15-0 jpeg line buffer read/write port bits [15:0] if yuv data is being input from the host, these bits are used as the jpeg line buffer read/write port. for all other modes, these bits have no hardware effect. when yuv data is input from host i/f (reg[0980] bits 3-1 = 001b or 101b), this port becomes the jpeg line buffer write port. when encoded yuv data is input from host i/f (reg[0980] bits 3-1 = 100b), this port becomes the jpeg line buffer write port. when decoded yuv data is output to host i/f (reg[0980] bits 3-1 = 100b), this port becomes the jpeg line buffer read port. table 10-57: line buffer address offset example horizontal size (xsize) k bytes reg[09d2h] value offset value area 640 30 42h 30800h 30800h - 37fffh reg[09e0h] jpeg line buffer read/write port register default = 0000h read/write jpeg line buffer read/write port bits 15-8 15 14 13 12 11 10 9 8 jpeg line buffer read/write port bits 7-0 76543210 free datasheet http:///
epson research and development page 235 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.17 interrupt control registers bit 5 sd card interrupt status (read only) this bit indicates the status of the sd card interrupt. this flag is masked by the sd card interrupt enable bit and is only available when reg[0a02h] bit 5 = 1). this bit is cleared when all sd card interrupt requests are cleared. when this bit = 0, a sd card interrupt has not occurred. when this bit = 1, a sd card interrupt has occurred. status flags must be read in reg[6100h] to determine the exact nature of the interrupt. bit 4 host interrupt status (read only) this bit indicates the status of the host interrupt. when this bit = 0, no host interrupt has occurred. when this bit = 1, a host interrupt has occurred. status flags must be read in reg[0a0ah] to determine the exact nature of the interrupt. bit 3 camera interrupt status (read only) this bit indicates the status of the camera interrupt. when this bit = 0, no camera interrupt has occurred. when this bit = 1, a camera interrupt has occurred. status flags must be read in reg[0116h] to determine the exact nature of the interrupt. bit 2 jpeg interrupt status (read only) this bit indicates the status of the jpeg interrupt. when this bit = 0, no jpeg interrupt has occurred. when this bit = 1, a jpeg interrupt has occurred. status flags must be read in reg[0982h] to determine the exact nature of the interrupt. bit 1 bitblt interrupt status (read only) this bit indicates the status of the bitblt interrupt. when this bit = 0, no bitblt interrupt has occurred. when this bit = 1, a bitblt interrupt has occurred. status flags must be read in reg[8030h] to determine the exact nature of the interrupt. bit 0 debug interrupt status (read only) this bit indicates the status of the debug interrupt. when this bit = 0, no debug interrupt has occurred. when this bit = 1, a debug interrupt has occurred. status flags must be read in reg[0a06h] to determine the exact nature of the interrupt. reg[0a00h] interrupt status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a sd card interrupt status host interrupt status camera interrupt status jpeg interrupt status bitblt interrupt status debug interrupt status 7 6543210 free datasheet http:///
page 236 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 5 sd card interrupt enable this bit controls the sd card interface interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 4 host interrupt enable this bit controls the host interface interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 3 camera interrupt enable this bit controls the camera interface interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 2 jpeg interrupt enable this bit controls the jpeg codec interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 1 bitblt interrupt enable this bit controls the bitblt interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 0 debug interrupt enable this bit controls the debug interrupt. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bit 5 sd card manual interrupt this bit manually sets a sd card interface interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. reg[0a02h] interrupt control register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a sd card interrupt enable host interrupt enable camera interrupt enable jpeg interrupt enable bitblt interrupt enable debug interrupt enable 7 6543210 reg[0a04h] interrupt control register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a sd card manual interrupt host manual interrupt camera manual interrupt jpeg manual interrupt bitblt manual interrupt debug manual interrupt 7 6543210 free datasheet http:///
epson research and development page 237 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 4 host manual interrupt this bit manually sets a host interface interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. bit 3 camera manual interrupt this bit manually sets a camera interface interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. bit 2 jpeg manual interrupt this bit manually sets a jpeg codec interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. bit 1 bitblt manual interrupt this bit manually sets a bitblt interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. bit 0 debug manual interrupt this bit manually sets a debug interrupt. when this bit = 0, the interrupt is cleared. when this bit = 1, the interrupt is asserted. bit 1 display fifo empty flag this flag is masked by reg[0a08h] bit 1 and indicates whether the panel interface has attempted to read data from the display fifo while it is empty. this flag can be used to generate an interrupt (int signal) to the host by setting both the display fifo empty interrupt enable (reg[0a08h] bit 1 = 1) and the debug interrupt enable (reg[0a02h] bit 0 = 1). for reads: when this bit = 0, the panel interface has not attempted to read data from the display fifo while it is empty. when this bit = 1, the panel interface has attempted to read data from the display fifo while it is empty. for writes: when this bit is written as 0, there is no hardware effect. when this bit is written as 1, the display fifo empty flag is cleared. reg[0a06h] debug status register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a display fifo empty flag yuv/rgb write buffer overflow flag 7 6 5 4 3 210 free datasheet http:///
page 238 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 yuv/rgb write buffer overflow flag for reads: when this bit = 0, no write buffer overflow has occurred. when this bit = 1, a write buffer overflow has occurred in the path from the yuv/rgb converter to the display buffer. for writes: when this bit is written as 0, there is no hardware effect. when this bit is written as 1, the yuv/rgb write buffer overflow flag is cleared. bit 1 display fifo empty interrupt enable this bit controls the display fifo empty interrupt. the status of this interrupt can be determined using the display fifo empty flag (reg[0a06h] bit 1). when this bit = 0, the display fifo empty interrupt is disabled. when this bit = 1, the display fifo empty interrupt is enabled bit 0 yuv/rgb write buffer overflow interrupt enable this bit controls the yuv/rgb write buffer overflow flag interrupt output. when this bit = 0, the yuv/rgb write buffer overflow interrupt is disabled. when this bit = 1, the yuv/rgb write buffer overflow interrupt is enabled reg[0a08h] interrupt control for debug register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a display fifo empty interrupt enable yuv/rgb write buffer overflow interrupt enable 7 6 5 4 3 210 free datasheet http:///
epson research and development page 239 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 15 cycle time out interrupt raw status this bit indicates the raw status of the cycle time out interrupt which happens when an access cycle to/from the jpeg fifo, jpeg line buffer, or bitblt fifo lasts longer than the specified time out value (reg[0a0eh] bits 4-0). if a cycle time out interrupt occurs and the cycle time out interrupt is enabled (reg[0a0ch] bit 15 = 1) and the host interrupt enable bit (reg[0a02h] bit 4) is set to 1, the int pin is asserted. when this bit = 0, a interrupt has not occurred. when this bit = 1, a cycle time out interrupt has occurred. to clear this bit, write a 1 to this bit. bit 5 bitblt fifo terminate write cycle interrupt raw status this bit indicates the status of the bitblt fifo terminate write cycle interrupt. when this bit = 0, no interrupt has occurred. when this bit = 1, a bitblt fifo terminate write cycle interrupt has occurred. to clear this bit, write this bit as 1. bit 4 bitblt fifo terminate read cycle interrupt raw status this bit indicates the status of the bitblt fifo terminate read cycle interrupt. when this bit = 0, no interrupt has occurred. when this bit = 1, a bitblt fifo terminate read cycle interrupt has occurred. to clear this bit, write this bit as 1. bit 3 jpeg line buffer terminate write cycle interrupt raw status this bit indicates the status of the jpeg line buffer terminate write cycle interrupt which happens when a write cycle attempts to write to the jpeg line buffer when it is full. when this happens, the cycle is terminated and no data is written to the jpeg line buffer. this interrupt is used to determine whether another write must be performed. if a jpeg line buffer terminate write cycle interrupt occurs and the jpeg line buffer terminate write cycle interrupt is enabled (reg[0a0ch] bit 3 = 1). and the host interrupt enable bit (reg[0a02h] bit 4) is set to 1, the int pin is asserted. when this bit = 0, a interrupt has not occurred. when this bit = 1, a jpeg line buffer terminate write cycle interrupt has occurred. to clear this bit, write a 1 to this bit. reg[0a0ah] host cycle interrupt status register default = 0000h read/write cycle time out interrupt raw status n/a 15 14 13 12 11 10 9 8 n/a bitblt fifo terminate write cycle interrupt raw status bitblt fifo terminate read cycle interrupt raw status jpeg line buffer terminate write cycle interrupt raw status jpeg line buffer terminate read cycle interrupt raw status jpeg fifo terminate write cycle interrupt raw status reserved 7 6543210 free datasheet http:///
page 240 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 2 jpeg line buffer terminate read cycle interrupt raw status this bit indicates the status of the jpeg line buffer terminate read cycle interrupt which happens when a read cycle attempts to read from the jpeg line buffer when it is empty. when this happens, the cycle is terminated and no data is read from the jpeg line buffer. this interrupt is used to determine whether another read must be performed. if a jpeg line buffer terminate read cycle interrupt occurs and the jpeg line buffer ter- minate read cycle interrupt is enabled (reg[0a0ch] bit 2 = 1), and the host interrupt enable bit (reg[0a02h] bit 4) is set to 1, the int pin is asserted. when this bit = 0, a interrupt has not occurred. when this bit = 1, a jpeg line buffer terminate read cycle interrupt has occurred. to clear this bit, write a 1 to this bit. bit 1 jpeg fifo terminate write cycle interrupt raw status this bit indicates the status of the jpeg fifo terminate write cycle interrupt which hap- pens when a write cycle attempts to write to the jpeg fifo when it is full. when this hap- pens, the cycle is terminated and no data is written to the jpeg fifo. this interrupt is used to determine whether another write must be performed. if a jpeg fifo terminate write cycle interrupt occurs and the jpeg fifo terminate write cycle interrupt is enabled (reg[0a0ch] bit 1 = 1), and the host interrupt enable bit (reg[0a02h] bit 4) is set to 1, the int pin is asserted. when this bit = 0, a interrupt has not occurred. when this bit = 1, a jpeg fifo terminate write cycle interrupt has occurred. to clear this bit, write a 1 to this bit. bit 0 reserved the default value for this bit is 0. bit 15 cycle time out interrupt enable when this bit is 0, the host interrupt request bit is not set. when this bit is 1, the host interrupt request bit is set. bit 5 bitblt fifo terminate write cycle interrupt enable when this bit is 0, the interrupt is disabled. when this bit is 1, the interrupt is enabled. bit 4 bitblt fifo terminate read cycle interrupt enable when this bit is 0, interrupt is disabled. when this bit is 1, interrupt is enabled. reg[0a0ch] host cycle interrupt control register default = 0000h read/write cycle time out interrupt enable n/a 15 14 13 12 11 10 9 8 n/a bitblt fifo terminate write cycle interrupt enable bitblt fifo terminate read cycle interrupt enable jpeg line buffer terminate write cycle interrupt enable jpeg line buffer terminate read cycle interrupt enable jpeg fifo terminate write cycle interrupt enable reserved 7 6543210 free datasheet http:///
epson research and development page 241 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 3 jpeg line buffer terminate write cycle interrupt enable when this bit is 0, the host interrupt request bit is not set. when this bit is 1, the host interrupt request bit is set. bit 2 jpeg line buffer terminate read cycle interrupt enable when this bit is 0, the host interrupt request bit is not set. when this bit is 1, the host interrupt request bit is set. bit 1 jpeg fifo terminate write cycle interrupt enable when this bit is 0, the host interrupt request bit is not set. when this bit is 1, the host interrupt request bit is set. bit 0 reserved the default value for this bit is 0. bit 7 immediate terminate cycle enable terminate cycles are used to terminate (or end) read/write cycles to the jpeg fifo (write only), jpeg line buffer and bitblt fifo. this bit in conjunction with the time out value bits (reg[0a0eh] bits 4-0) determines when a terminate cycle is generated. the following tables summarizes the conditions that cause a terminate cycle to be generated. note when the immediate terminate cycle function is enabled (reg[0a0eh] bit 7 = 1), the time out value bits (reg[0a0eh] bits 4-0) must be set to 1fh. reg[0a0eh] cycle time out control register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 immediate terminate cycle enable n/a time out value bits 4-0 7 6 543210 table 10-58: terminate cycle generation summary reg[0a0eh] bit 7 reg[0a0eh] bits 4-0 terminate cycle generation 0 = 11111b if a write to a full jpeg fifo/line buffer/bitblt fifo or a read from an empty jpeg line buffer/bitblt fifo is attempted, a terminate cycle is generated once the time out value of 1fh is exceeded. 11111b if a write to a full jpeg fifo/line buffer/bitblt fifo or a read from an empty jpeg line buffer/bitblt fifo is attempted, a terminate cycle is generated once the time out value is exceeded. 1 = 11111b if a write to a full jpeg fifo/line buffer/bitblt fifo or a read from an empty jpeg line buffer/bitblt fifo is attempted, a terminate cycle is generated immediately. if a write access to a full jpeg fifo/line buffer/bitblt fifo or a read access from a jpeg line buffer/bitblt fifo exceeds the time out value (reg[0a0eh] bits 4-0) of 1fh, a terminate cycle is generated immediately. free datasheet http:///
page 242 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 4-0 time out value bits[4:0] these bits control the length of time (time out value) allowed for an access cycle to the jpeg fifo, jpeg line buffer, or bitblt fifo to take place before a terminate cycle is generated. the time out value is specified as follows and should be configured to a default value of 1fh at initialization. reg[0a0eh] bits 4-0 = time out value in clks time out value = internal system clock 2 reg[0a10h] is reserved this register is reserved and should not be written. bit 5 sd card interrupt request status (read only) this bit indicates a sd card interrupt request has taken place. this bit is not masked by the corresponding interrupt enable bit in reg[0a02h]. when this bit = 0, a sd card interrupt has not occurred. when this bit = 1, a sd card interrupt has occurred. interrupt request flags must be read in reg[6100h] to determine the exact nature of the interrupt. bit 4 host interface interrupt request status (read only) when this bit = 0, a host interface interrupt has not occurred. when this bit = 1, a host interface interrupt request has occurred. bit 3 camera interrupt request status (read only) when this bit = 0, a camera interrupt request has not occurred. when this bit = 1, a camera interrupt request has occurred. bit 2 jpeg interrupt request status (read only) when this bit = 0, a jpeg interrupt request has not occurred. when this bit = 1, a jpeg interrupt request has occurred. bit 1 bitblt interrupt request status (read only) when this bit = 0, a bitblt interrupt request has not occurred. when this bit = 1, a bitblt interrupt request has occurred. bit 0 debug interrupt request status (read only) when this bit = 0, a debug interrupt request has not occurred. when this bit = 1, a debug interrupt request has occurred. reg[0a40h] interrupt request status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a sd card interrupt request status host interface interrupt request status camera interrupt request status jpeg interrupt request status bitblt interrupt request status debug interrupt request status 7 6543210 free datasheet http:///
epson research and development page 243 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.18 jpeg encode performance register bit 0 jpeg encode high speed mode when this bit = 0, the jpeg encoding process runs in ?high speed mode?. when this bit = 1, the jpeg encoding process runs in ?normal mode? (default). when high speed mode is enabled, the huffman tables must be programmed according to the tables specified in the iso/iec is 10918-1 annex k in the itu-t recommendation t.81 book k. for recommended values see the bit descriptions for the huffman tables (reg[1400h] - [17a2h]. reg[0f00h] jpeg encode performance register default = 0001h read/write n/a 15 14 13 12 11 10 9 8 n/a jpeg encode high speed mode 7 6 5 4 3 2 10 free datasheet http:///
page 244 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 10.4.19 jpeg codec registers bit 7 reserved the default value for this bit is 0. bit 4 reserved the default value for this bit is 0. bit 3 marker insert enable this bit determines if the marker (see reg[1020h] - [1066h]) is inserted during jpeg encoding. during jpeg decoding this bit is ignored. when this bit = 0, the marker is not inserted. when this bit = 1, the entire marker is inserted into the jpeg file. note when the marker is inserted, the entire 36 byte marker (reg[1020h] - [1066h]) is in- serted into the jpeg file regardless of what value the marker length bits (reg[1024h] - [1026h]) specify. bit 2 jpeg operation select this bit selects the jpeg operation and the input source for the resizer block. this bit should be set to 0 when resizing data from the camera. this bit must be cleared before the jpeg module is disabled (reg[0980h] bit 0 = 0). reg[1000h] operation mode setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 reserved n/a reserved marker insert enable jpeg operation select yuv format select bits 1-0 7 6 543210 table 10-59: jpeg operation selection reg[1000h] bit 2 jpeg operation resizer source 0 encode camera data / memory image data / host data 1 decode jpeg decoded data free datasheet http:///
epson research and development page 245 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 1-0 yuv format select bits[1:0] these bits select the yuv format of the jpeg codec. for the jpeg encode process, these bits must be set to the desired yuv format. for the jpeg decode process, these bits are read only and indicate the yuv format of the data being decoded. note only yuv 4:2:0 and yuv 4:2:2 are supported for host input jpeg decode/encode. note this register is write only. reading this register may cause the jpeg codec to be- have unexpectedly. note when the jpeg codec is working, this register must not be written to, except to perform a jpeg codec software reset. bit 7 jpeg codec software reset (write only) this bit initiates a software reset of the jpeg codec. the jpeg codec registers (reg[1000h]-[17a2h]) are not affected. when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the jpeg codec is reset. bit 0 jpeg operation start (write only) this bit is used to begin a jpeg operation. when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the jpeg operation is started. table 10-60: yuv format selection reg[1000h] bits 1-0 yuv format 00b 4:4:4 (decode only) 01b 4:2:2 (encode/decode) 10b 4:2:0 (encode/decode) 11b 4:1:1 (encode/decode) reg[1002h] command setting register default = not applicable write only n/a 15 14 13 12 11 10 9 8 jpeg codec sw reset n/a jpeg operation start 7 6 5 4 3 2 10 free datasheet http:///
page 246 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 jpeg operation status (read only) this bit indicates the state of the jpeg codec and clears the jpeg codec interrupt (reg[0982h] bit 1) when read. when this bit = 0, the jpeg codec is idle. when this bit = 1, the jpeg codec is busy (a decode or encode operation is in progress). bit 2 color 3 table select when this bit = 0, the color 3 table uses quantization table no. 0 (reg[1200-127eh]. when this bit = 1, the color 3 table uses quantization table no. 1 (reg[1280-12feh]. bit 1 color 2 table select when this bit = 0, the color 2 table uses quantization table no. 0 (reg[1200-127eh]. when this bit = 1, the color 2 table uses quantization table no. 1 (reg[1280-12feh]. bit 0 color 1 table select when this bit = 0, the color 1 table uses quantization table no. 0 (reg[1200-127eh]. when this bit = 1, the color 1 table uses quantization table no. 1 (reg[1280-12feh]. reg[1004h] jpeg operation status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 n/a jpeg operation status (ro) 7 6 5 4 3 2 10 reg[1006h] quantization table number register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a color 3 table select color 2 table select color 1 table select 7 6 5 4 3210 free datasheet http:///
epson research and development page 247 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 5 ac color 3 table select when this bit = 0, the ac color 3 table uses the ac huffman table no. 0 (reg[1440- 145eh] and reg[1460-15a2h]). when this bit = 1, the ac color 3 table uses the ac huffman table no. 1 (reg[1640- 165eh] and reg[1660-17a2h]). bit 4 dc color 3 table select when this bit = 0, the dc color 3 table uses the dc huffman table no. 0 (reg[1400- 141eh] and reg[1420-1436h]). when this bit = 1, the dc color 3 table uses the dc huffman table no. 1 (reg[1600- 161eh] and reg[1620-1636h]). bit 3 ac color 2 table select when this bit = 0, the ac color 2 table uses the ac huffman table no. 0 (reg[1440- 145eh] and reg[1460-15a2h]). when this bit = 1, the ac color 2 table uses the ac huffman table no. 1 (reg[1640- 165eh] and reg[1660-17a2h]). bit 2 dc color 2 table select when this bit = 0, the dc color 2 table uses the dc huffman table no. 0 (reg[1400- 141eh] and reg[1420-1436h]). when this bit = 1, the dc color 2 table uses the dc huffman table no. 1 (reg[1600- 161eh] and reg[1620-1636h]). bit 1 ac color 1 table select when this bit = 0, the ac color 1 table uses the ac huffman table no. 0 (reg[1440- 145eh] and reg[1460-15a2h]). when this bit = 1, the ac color 1 table uses the ac huffman table no. 1 (reg[1640- 165eh] and reg[1660-17a2h]). bit 0 dc color 1 table select when this bit = 0, the dc color 1 table uses the dc huffman table no. 0 (reg[1400- 141eh] and reg[1420-1436h]). when this bit = 1, the dc color 1 table uses the dc huffman table no. 1 (reg[1600- 161eh] and reg[1620-1636h]). reg[1008h] huffman table number register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a ac color 3 table select dc color 3 table select ac color 2 table select dc color 2 table select ac color 1 table select dc color 1 table select 7 6543210 free datasheet http:///
page 248 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[100ah] bits 7-0 reg[100ch] bits 7-0 dri value bits [15:0] these bits determine the mcu number for rst marker insertion during encoding. during decoding, these bits are ignored. the dri value bits must be set when jpeg 180 rotation encode is enabled (reg[0980h] bit 8 = 1). the dri (designated restart interval) value must be set as follows. dri = image width / horizontal mcu size where: mcu size depends on the yuv format (reg[1000h] bits 1-0) as follows reg[100ah] dri setting register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 dri value bits 15-8 76543210 reg[100ch] dri setting register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 dri value bits 7-0 76543210 table 10-61: mcu size reg[1000h] bits 1-0 yuv format mcu size (horizontal x vertical) 00b reserved reserved 01b 4:2:2 16 x 8 10b 4:2:0 16 x 16 11b 4:1:1 32 x 8 free datasheet http:///
epson research and development page 249 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[100eh] bits 7-0 reg[1010h] bits 7-0 y pixel size bits[15:0] for the jpeg encode process, these bits specify the vertical image size before encoding takes place. for the jpeg decode process, these bits are read-only and indicate the vertical image size. the following restrictions must be observed when setting the vertical pixel size. the minimum resolution must be set based on the yuv format as follows. note for all processes (jpeg encode/decode and yuv capture/display) the following formu- la must be valid. vertical pixel size > 1 reg[100eh] vertical pixel size register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 y pixel size bits 15-8 76543210 reg[1010h] vertical pixel size register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 y pixel size bits 7-0 76543210 table 10-62: vertical pixel size minimum resolution restrictions yuv format minimum resolution 4:4:4 (decode only) 1x1 4:2:2 (encode/decode) 2x1 4:2:0 (encode/decode) 2x2 4:1:1 (encode/decode) 4x1 free datasheet http:///
page 250 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[1012h] bits 7-0 reg[1014h] bits 7-0 x pixel size bits[15:0] for the jpeg encode process, these bits specify the horizontal image size before encoding takes place. for the jpeg decode process, these bits are read-only and indicate the horizontal image size. the following restrictions must be observed when setting the vertical pixel size. the minimum resolution must be set based on the yuv format as follows. reg[1012h] horizontal pixel size register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 x pixel size bits 15-8 76543210 reg[1014h] horizontal pixel size register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 x pixel size bits 7-0 76543210 table 10-63: horizontal pixel size minimum resolution restrictions yuv format minimum resolution minimum horizontal pixel size 4:2:2 2x1 2 4:2:0 2x2 16 4:1:1 4x1 4 free datasheet http:///
epson research and development page 251 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[1018h] bits 7-0 reg[1016h] bits 7-0 dnl value bits[15:0] for the jpeg decode process, these bits are read-only and indicate the dnl (define number of lines) value for the decoded jpeg file. for the jpeg encode process, these bits are not used. reg[101ah] is reserved this register is reserved and should not be written. reg[1016h] dnl value setting register 0 default = 0000h read only n/a 15 14 13 12 11 10 9 8 dnl value bits 15-8 76543210 reg[1018h] dnl value setting register 1 default = 0000h read only n/a 15 14 13 12 11 10 9 8 dnl value bits 7-0 76543210 free datasheet http:///
page 252 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 1-0 rst marker operation select bits[1:0] for the jpeg decode process, these bits select the rst marker operation. for the jpeg encode process, these bits are not used. reg[101ch] rst marker operation setting register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a rst marker operation select bits 1-0 7 6 5 4 3 210 table 10-64: rst marker selection reg[101ch] bits 1-0 rst marker operation 00b error detection and data revise function is turned off this option should only be used when it is certain that the jpeg file to be decoded is correct and has no errors. if there is an error in the file, no error detection will take place and the decode process will not finish correctly. 01b error detection on when an error is detected during the decode process, the decode process finishes and the jpeg interrupt is asserted (reg[0a00h] bit 2 = 1). to determine the exact nature of the operational error see reg[0982h]. to determine the jpeg decode error (file error), check the jpeg error status bits (reg[101eh] bits 6-3). because the decode process finished before normal completion, all data can not be displayed. if the jpeg file is to be decoded again with the data revise function on, a software reset is required (see reg[1002h] bit 7). 10b data revise function on when an error is detected during the decode process, data is skipped/added automatically and the decode process continues normally to the end of file. after the decode process finishes, a data revise interrupt is asserted. because the decode process is finished completely, the next jpeg file can be decoded immediately. 11b reserved free datasheet http:///
epson research and development page 253 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 7 revise code (read only) this bit is valid only when the data revise function is enabled using the rst marker selection bits (reg[101ch bits 1-0 = 10b). for the jpeg decode process, this bit indicates whether a revise operation has been done. for the jpeg encode process, this bit is not used. when this bit = 0, a revise operation was not done. when this bit = 1, a revise operation was done. bits 6-3 jpeg error status[3:0] (read only) these bits are valid only when error detection is enabled using the rst marker selection bits (reg[101ch bits 1-0 = 01b). for the jpeg decode process, these bits indicate the type of jpeg error. if these bits return 0000b, no error has occurred. for the jpeg encode process, these bits are not used. reg[101eh] rst marker operation status register default = 0000h read only n/a 15 14 13 12 11 10 9 8 revise code jpeg error status bits 3-0 n/a 76543 2 1 0 table 10-65: jpeg error status reg[101eh] bits 6-3 jpeg error status 0000b no error 0001b - 1010b reserved 1011b restart interval error 1100b image size error 1101b - 1111b reserved free datasheet http:///
page 254 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[1020h-1066h] these registers (36 bytes) store the insertion marker data which gets inserted into the jpeg file. only the even bytes are used. all unused registers (up to reg[1200h]) should be filled with ffh. the registers are defined as follows. reg[1200-127eh] quantization table no. 0 these registers are used for the jpeg encode process only. reg[1280-12feh] quantization table no. 1 these registers are used for the jpeg encode process only. reg[1020 - 1066h] insertion marker data register default = 00ffh read/write n/a 15 14 13 12 11 10 9 8 insert marker data bits 7-0 76543210 table 10-66: insertion marker data register usage register description reg[1020h]-[1022h] these registers set the insertion marker code type. reg[1024h]-[1026h] these registers set the marker length (0002h - 0022h). reg[1028h]-[1066h] these registers set the marker data (up to a maximum of 32 bytes). note that all unused registers must be filled with ffh. reg[1200 - 127eh] quantization table no. 0 register default = not applicable read/write n/a 15 14 13 12 11 10 9 8 quantization table no. 0 bits 7-0 76543210 reg[1280 - 12feh] quantization table no. 1 register default = not applicable write only n/a 15 14 13 12 11 10 9 8 quantization table no. 1 bits 7-0 76543210 free datasheet http:///
epson research and development page 255 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[1400-141eh] dc huffman table no. 0 (write only) these registers are used for the jpeg encode process only and set the codes for code length. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the dc huffman table no. 0 must be programmed as follows. reg[1420-1436h] dc huffman table no. 0 (write only) these registers are used for the jpeg encode process only and set a group number based on the order of probability of occurrence. only bits 3-0 are used (bits 7-4 must be set to 0). when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the dc huffman table no. 0 must be programmed as follows. reg[1400 - 141eh] dc huffman table no. 0 register 0 default = not applicable write only n/a 15 14 13 12 11 10 9 8 dc huffman table no. 0 register 0 bits 7-0 76543210 table 10-67: dc huffman table no. 0 values for high speed mode register value register value register value register value reg[1400h] 00h reg[1408h] 01h reg[1410h] 01h reg[1418h] 00h reg[1402h] 01h reg[140ah] 01h reg[1412h] 00h reg[141ah] 00h reg[1404h] 05h reg[140ch] 01h reg[1414h] 00h reg[141ch] 00h reg[1406h] 01h reg[140eh] 01h reg[1416h] 00h reg[141eh] 00h reg[1420 - 1436h] dc huffman table no. 0 register 1 default = not applicable write only n/a 15 14 13 12 11 10 9 8 reserved (must be all 0) dc huffman table no. 0 register 1 bits 3-0 76543210 table 10-68: dc huffman table no. 1 values for high speed mode register value register value register value register value reg[1420h] 00h reg[1426h] 03h reg[142ch] 06h reg[1432h] 09h reg[1422h] 01h reg[1428h] 04h reg[142eh] 07h reg[1434h] 0ah reg[1424h] 02h reg[142ah] 05h reg[1430h] 08h reg[1436h] 0bh free datasheet http:///
page 256 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[1440-145eh] ac huffman table no. 0 (write only) these registers are used for the jpeg encode process only and set the codes for code length. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the ac huffman table no. 0 must be programmed as follows. reg[1460-15a2h] ac huffman table no. 0 (write only) these registers are used for the jpeg encode process only and set a zero run length / group number based on the order of probability of occurrence. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the ac huffman table no. 0 must be programmed as follows. reg[1440 - 145eh] ac huffman table no. 0 register 0 default = not applicable write only n/a 15 14 13 12 11 10 9 8 ac huffman table no. 0 register 0 bits 7-0 76543210 table 10-69: ac huffman table no. 0 values for high speed mode register value register value register value register value reg[1440h] 00h reg[1448h] 03h reg[1450h] 05h reg[1458h] 00h reg[1442h] 02h reg[144ah] 02h reg[1452h] 05h reg[145ah] 00h reg[1444h] 01h reg[144ch] 04h reg[1454h] 04h reg[145ch] 01h reg[1446h] 03h reg[144eh] 03h reg[1456h] 04h reg[145eh] 7dh reg[1460 - 15a2h] ac huffman table no. 0 register 1 default = not applicable write only n/a 15 14 13 12 11 10 9 8 ac huffman table no. 0 register 0 bits 7-0 76543210 free datasheet http:///
epson research and development page 257 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential table 10-70: ac huffman table no. 0 values for high speed mode register value register value register value register value reg[1460h] 01h reg[14b0h] 17h reg[1500h] 6ah reg[1550h] b7h reg[1462h] 02h reg[14b2h] 18h reg[1502h] 73h reg[1552h] b8h reg[1464h] 03h reg[14b4h] 19h reg[1504h] 74h reg[1554h] b9h reg[1466h] 00h reg[14b6h] 1ah reg[1506h] 75h reg[1556h] bah reg[1468h] 04h reg[14b8h] 25h reg[1508h] 76h reg[1558h] c2h reg[146ah] 11h reg[14bah] 26h reg[150ah] 77h reg[155ah] c3h reg[146ch] 05h reg[14bch] 27h reg[150ch] 78h reg[155ch] c4h reg[146eh] 12h reg[14beh] 28h reg[150eh] 79h reg[155eh] c5h reg[1470h] 21h reg[14c0h] 29h reg[1510h] 7ah reg[1560h] c6h reg[1472h] 31h reg[14c2h] 2ah reg[1512h] 83h reg[1562h] c7h reg[1474h] 41h reg[14c4h] 34h reg[1514h] 84h reg[1564h] c8h reg[1476h] 06h reg[14c6h] 35h reg[1516h] 85h reg[1566h] c9h reg[1478h] 13h reg[14c8h] 36h reg[1518h] 86h reg[1568h] cah reg[147ah] 51h reg[14cah] 37h reg[151ah] 87h reg[156ah] d2h reg[147ch] 61h reg[14cch] 38h reg[151ch] 88h reg[156ch] d3h reg[147eh] 07h reg[14ceh] 39h reg[151eh] 89h reg[156eh] d4h reg[1480h] 22h reg[14d0h] 3ah reg[1520h] 8ah reg[1570h] d5h reg[1482h] 71h reg[14d2h] 43h reg[1522h] 92h reg[1572h] d6h reg[1484h] 14h reg[14d4h] 44h reg[1524h] 93h reg[1574h] d7h reg[1486h] 32h reg[14d6h] 45h reg[1526h] 94h reg[1576h] d8h reg[1488h] 81h reg[14d8h] 46h reg[1528h] 95h reg[1578h] d9h reg[148ah] 91h reg[14dah] 47h reg[152ah] 96h reg[157ah] dah reg[148ch] a1h reg[14dch] 48h reg[152ch] 97h reg[157ch] e1h reg[148eh] 08h reg[14deh] 49h reg[152eh] 98h reg[157eh] e2h reg[1490h] 23h reg[14e0h] 4ah reg[1530h] 99h reg[1580h] e3h reg[1492h] 42h reg[14e2h] 53h reg[1532h] 9ah reg[1582h] e4h reg[1494h] b1h reg[14e4h] 54h reg[1534h] a2h reg[1584h] e5h reg[1496h] c1h reg[14e6h] 55h reg[1536h] a3h reg[1586h] e6h reg[1498h] 15h reg[14e8h] 56h reg[1538h] a4h reg[1588h] e7h reg[149ah] 52h reg[14eah] 57h reg[153ah] a5h reg[158sh] e8h reg[149ch] d1h reg[14ech] 58h reg[153ch] a6h reg[158ch] e9h reg[149eh] f0h reg[14eeh] 59h reg[153eh] a7h reg[158eh] eah reg[14a0h] 24h reg[14f0h] 5ah reg[1540h] a8h reg[1590h] f1h reg[14a2h] 33h reg[14f2h] 63h reg[1542h] a9h reg[1592h] f2h reg[14a4h] 62h reg[14f4h] 64h reg[1544h] aah reg[1594h] f3h reg[14a6h] 72h reg[14f6h] 65h reg[1546h] b2h reg[1596h] f4h reg[14a8h] 82h reg[14f8h] 66h reg[1548h] b3h reg[1598h] f5h reg[14aah] 09h reg[14fah] 67h reg[154ah] b4h reg[159ah] f6h reg[14ach] 0ah reg[14fch] 68h reg[154ch] b5h reg[159ch] f7h reg[14aeh] 16h reg[14feh] 69h reg[154eh] b6h reg[159eh] f8h reg[15a0h] f9h reg[15a2h] fah free datasheet http:///
page 258 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[1600-161eh] dc huffman table no. 1 (write only) these registers are used for the jpeg encode process only and set the codes for code length. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the dc huffman table no. 1 must be programmed as follows. reg[1620-1636h] dc huffman table no. 1 (write only) these registers are used for the jpeg encode process only and set a group number based on the order of probability of occurrence. only bits 3-0 are used (bits 7-4 must be set to 0). when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the dc huffman table no. 1 must be programmed as follows. reg[1600 - 161eh] dc huffman table no. 1 register 0 default = not applicable write only n/a 15 14 13 12 11 10 9 8 dc huffman table 1 register no. 0 bits 7-0 76543210 table 10-71: dc huffman table no. 1 values for high speed mode register value register value register value register value reg[1600h] 00h reg[1608h] 01h reg[1610h] 01h reg[1618h] 00h reg[1602h] 03h reg[160ah] 01h reg[1612h] 01h reg[161ah] 00h reg[1604h] 01h reg[160ch] 01h reg[1614h] 01h reg[161ch] 00h reg[1606h] 01h reg[160eh] 01h reg[1616h] 00h reg[161eh] 00h reg[1620 - 1636h] dc huffman table no. 1 register 1 default = not applicable write only n/a 15 14 13 12 11 10 9 8 reserved (must be all 0) dc huffman table no. 1 register 1 bits 3-0 76543210 table 10-72: dc huffman table no. 1 values for high speed mode register value register value register value register value reg[1620h] 00h reg[1626h] 03h reg[162ch] 06h reg[1632h] 09h reg[1622h] 01h reg[1628h] 04h reg[162eh] 07h reg[1634h] 0ah reg[1624h] 02h reg[162ah] 05h reg[1630h] 08h reg[1636h] 0bh free datasheet http:///
epson research and development page 259 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[1640-165eh] ac huffman table no. 1 (write only) these registers are used for the jpeg encode process only and set the codes for code length. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the ac huffman table no. 1 must be programmed as follows. reg[1660-17a2h] ac huffman table no. 1 (write only) these registers are used for the jpeg encode process only and set a zero run length / group number based on the order of probability of occurrence. when jpeg encode ?high speed mode? is enabled (reg[0f00h] bit 0 = 0), the ac huffman table no. 1 must be programmed as follows. reg[1640 - 165eh] ac huffman table no. 1 register 0 default = not applicable write only n/a 15 14 13 12 11 10 9 8 ac huffman table no. 1 register 0 bits 7-0 76543210 table 10-73: ac huffman table no. 1 values for high speed mode register value register value register value register value reg[1640h] 00h reg[1648h] 04h reg[1650h] 07h reg[1658h] 00h reg[1642h] 02h reg[164ah] 04h reg[1652h] 05h reg[165ah] 01h reg[1644h] 01h reg[164ch] 03h reg[1654h] 04h reg[165ch] 02h reg[1646h] 02h reg[164eh] 04h reg[1656h] 04h reg[165eh] 77h reg[1660 - 17a2h] ac huffman table no. 1 register 1 default = not applicable write only n/a 15 14 13 12 11 10 9 8 ac huffman table no. 1 register 0 bits 7-0 76543210 free datasheet http:///
page 260 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 10-74: ac huffman table no. 1 values for high speed mode register value register value register value register value reg[1660h] 00h reg[16b0h] e1h reg[1700h] 69h reg[1750h] b5h reg[1662h] 01h reg[16b2h] 25h reg[1702h] 6ah reg[1752h] b6h reg[1664h] 02h reg[16b4h] f1h reg[1704h] 73h reg[1754h] b7h reg[1666h] 03h reg[16b6h] 17h reg[1706h] 74h reg[1756h] b8h reg[1668h] 11h reg[16b8h] 18h reg[1708h] 75h reg[1758h] b9h reg[166ah] 04h reg[16bah] 19h reg[170ah] 76h reg[175ah] bah reg[166ch] 05h reg[16bch] 1ah reg[170ch] 77h reg[175ch] c2h reg[166eh] 21h reg[16beh] 26h reg[170eh] 78h reg[175eh] c3h reg[1670h] 31h reg[16c0h] 27h reg[1710h] 79h reg[1760h] c4h reg[1672h] 06h reg[16c2h] 28h reg[1712h] 7ah reg[1762h] c5h reg[1674h] 12h reg[16c4h] 29h reg[1714h] 82h reg[1764h] c6h reg[1676h] 41h reg[16c6h] 2ah reg[1716h] 83h reg[1766h] c7h reg[1678h] 51h reg[16c8h] 35h reg[1718h] 84h reg[1768h] c8h reg[167ah] 07h reg[16cah] 36h reg[171ah] 85h reg[176ah] c9h reg[167ch] 61h reg[16cch] 37h reg[171ch] 86h reg[176ch] cah reg[167eh] 71h reg[16ceh] 38h reg[171eh] 87h reg[176eh] d2h reg[1680h] 13h reg[16d0h] 39h reg[1720h] 88h reg[1770h] d3h reg[1682h] 22h reg[16d2h] 3ah reg[1722h] 89h reg[1772h] d4h reg[1684h] 32h reg[16d4h] 43h reg[1724h] 8ah reg[1774h] d5h reg[1686h] 81h reg[16d6h] 44h reg[1726h] 92h reg[1776h] d6h reg[1688h] 08h reg[16d8h] 45h reg[1728h] 93h reg[1778h] d7h reg[168ah] 14h reg[16dah] 46h reg[172ah] 94h reg[177ah] d8h reg[168ch] 42h reg[16dch] 47h reg[172ch] 95h reg[177ch] d9h reg[168eh] 91h reg[16deh] 48h reg[172eh] 96h reg[177eh] dah reg[1690h] a1h reg[16e0h] 49h reg[1730h] 97h reg[1780h] e2h reg[1692h] b1h reg[16e2h] 4ah reg[1732h] 98h reg[1782h] e3h reg[1694h] c1h reg[16e4h] 53h reg[1734h] 99h reg[1784h] e4h reg[1696h] 09h reg[16e6h] 54h reg[1736h] 9ah reg[1786h] e5h reg[1698h] 23h reg[16e8h] 55h reg[1738h] a2h reg[1788h] e6h reg[169ah] 33h reg[16eah] 56h reg[173ah] a3h reg[178ah] e7h reg[169ch] 52h reg[16ech] 57h reg[173ch] a4h reg[178ch] e8h reg[169eh] f0h reg[16eeh] 58h reg[173eh] a5h reg[178eh] e9h reg[16a0h] 15h reg[16f0h] 59h reg[1740h] a6h reg[1790h] eah reg[16a2h] 62h reg[16f2h] 5ah reg[1742h] a7h reg[1792h] f2h reg[16a4h] 72h reg[16f4h] 63h reg[1744h] a8h reg[1794h] f3h reg[16a6h] d1h reg[16f6h] 64h reg[1746h] a9h reg[1796h] f4h reg[16a8h] 0ah reg[16f8h] 65h reg[1748h] aah reg[1798h] f5h reg[16aah] 16h reg[16fah] 66h reg[174ah] b2h reg[179ah] f6h reg[16ach] 24h reg[16fch] 67h reg[174ch] b3h reg[179ch] f7h reg[16aeh] 34h reg[16feh] 68h reg[174eh] b4h reg[179eh] f8h reg[17a0h] f9h reg[17a2h] fah free datasheet http:///
epson research and development page 261 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.20 sd memory card interface registers bit 8 reserved the default value for this bit is 0. bit 3 sd memory card software reset (write only) this bit performs a software reset of the sd memory card interface and resets reg[6100h] - reg[613eh]. when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, a software reset is performed. bits 2-1 reserved the default value for these bits is 0. bit 0 sd memory card interface enable this bit enables the sd memory card interface. when the interface is disabled, reg[6100h] - reg[613eh] are inaccessible. when this bit = 0, the sd memory card interface is disabled (default). when this bit = 1, the sd memory card interface is enabled. note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. reg[6000h] sd memory card configuration register 0 default = 0000h read/write n/a reserved 15 14 13 12 11 10 9 8 n/a sd memory card software reset (wo) reserved sd memory card interface enable 7 6 5 4 3 2 1 0 free datasheet http:///
page 262 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 7 sddat3 pull-down control this bit controls the pull-down resistance for the sddat3 pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 6 sddat2 pull-down control this bit controls the pull-down resistance for the sddat2 pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 5 sddat1 pull-down control this bit controls the pull-down resistance for the sddat1 pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. reg[6002h] sd memory card configuration register 1 default = 00ffh read/write n/a 15 14 13 12 11 10 9 8 sddat3 pull- down control sddat2 pull- down control sddat1 pull- down control sddat0 pull- down control sdcmd pull- down control sdclk pull-down control sdwp pull-down control sdcd# pull-down control 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 263 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 4 sddat0 pull-down control this bit controls the pull-down resistance for the sddat0 pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 3 sdcmd pull-down control this bit controls the pull-down resistance for the sdcmd pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 2 sdclk pull-down control this bit controls the pull-down resistance for the sdclk pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 1 sdwp pull-down control this bit controls the pull-down resistance for the sdwp pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. free datasheet http:///
page 264 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 sdcd# pull-down control this bit controls the pull-down resistance for the sdcd# pin. when this bit = 0, the pull-down resistance is disabled. when this bit = 1, the pull-down resistance is enabled (default). note when the sd memory card interface is not used (reg[6000h] bit 0 = 0), the sdcard pins must be left unconnected and the pulldown resistance must be enabled (reg[6002h] bit bits 7-0 = 1) to avoid unnecessary current draw. if the sd memory card interface interface is used (reg[6000h] bit 0 = 1), the pulldown resistance must be disabled (reg[6002h] bit bits 7-0 = 0) immediately to avoid unnecessary current draw. bit 7 sddat3 status when sddat3 is an input, this bit indicates the status of sddat3. for reads: when this bit returns a 0, sddat3 input is low. when this bit returns a 1, sddat3 input is high. for writes: writing to this bit has no hardware effect. bit 6 sddat2 status when sddat2 is an input, this bit indicates the status of sddat2. for reads: when this bit returns a 0, sddat2 input is low. when this bit returns a 1, sddat2 input is high. for writes: writing to this bit has no hardware effect. bit 5 sddat1 status when sddat1 is an input, this bit indicates the status of sddat1. for reads: when this bit returns a 0, sddat1 input is low. when this bit returns a 1, sddat1 input is high. for writes: writing to this bit has no hardware effect. reg[6004h] sd memory card configuration register 2 default = xxxxh read/write n/a 15 14 13 12 11 10 9 8 sddat3 status sddat2 status sddat1 status sddat0 status sdcmd status sdclk status sdwp status (ro) sdcd# status (ro) 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 265 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 4 sddat0 status when sddat0 is an input, this bit indicates the status of sddat0. for reads: when this bit returns a 0, sddat0 input is low. when this bit returns a 1, sddat0 input is high. for writes: writing to this bit has no hardware effect. bit 3 sdcmd status when sdcmd is an input, this bit indicates the status of sdcmd. for reads: when this bit returns a 0, sdcmd input is low. when this bit returns a 1, sdcmd input is high. for writes: writing to this bit has no hardware effect. bit 2 sdclk status when the sdclk is an input, this bit indicates the status of sdclk. for reads: when this bit returns a 0, sdclk input is low. when this bit returns a 1, sdclk input is high. for writes: writing to this bit has no hardware effect. bit 1 sdwp status (read only) this bit indicates the status of sdwp. when this bit returns a 0, sdwp input is low. when this bit returns a 1, sdwp input is high. bit 0 sdcd# status (read only) this bit indicates the status of sdcd#. when this bit returns a 0, sdcd# input is low. when this bit returns a 1, sdcd# input is high. free datasheet http:///
page 266 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 7-4 sdclk divide select bits [3:0] these bits select the divide ratio for the sd memory card clock (sdclk signal). the clock source for the sd memory card clock is the system clock. when the divide ratio is changed, write a 1 to the sdclk change start bit (reg[6104h] bit 7 = 1) and wait for the change to take effect (reg[6104h] bit 7 = 0) before using the sd memory clock inter- face. note sd memory card clock divide ratio must be configured such that the resulting sd- clk frequency does not exceed 13.75mhz (see section 7.7.2, ?sd memory card clock output? on page 105). the following table provides some examples of typical sd memory card clock configura- tions. reg[6100h] sd memory card control register 0 default = 0031h read/write n/a 15 14 13 12 11 10 9 8 sdclk divide select bits 3-0 reserved sd card interrupt enable sd card interrupt flag 7 6 5 4 3 2 1 0 table 10-75: sd memory card clock divide ratio selection reg[6100h] bits 7-4 sd memory card clock divide ratio 0000b reserved 0001b 2:1 (see note) 0010b 3:1 (see note) 0011b (default) 4:1 0101b 62:1 0110b through 1000b reserved 1001b 130:1 1010b 131:1 1011b through 1101b reserved 1110b 255:1 1111b 256:1 table 10-76: system clock frequency and sd card clock system clock frequency reg[6100h] bits 7-4 identification mode data transfer mode ~52mhz 1010 (~396khz) 0011 (~13mhz) ~55mhz 1110 (~215khz) 0011 (~13.75mhz max) free datasheet http:///
epson research and development page 267 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 3-2 reserved the default value for these bits is 0. bit 1 sd card interrupt enable this bit controls the sd memory card interrupt (sdcd#) and masks the sd card inter- rupt status bit (reg[0a00h] bit 7). when this bit = 0, the interrupt is disabled (default). when this bit = 1, the interrupt is enabled. bit 0 sd card interrupt flag this bit indicates that a sd card interrupt has occurred (change in card detect, sdcd#). this bit is not masked by the sd card interrupt enable bit (reg[6100h] bit 1). for reads: when this bit returns a 0, the interrupt has not occurred. when this bit returns a 1, the interrupt has occurred (sdcd# signal has changed). for writes: when a 0 is written to this bit, the flag is cleared. when a 1 is written to this bit, there is no hardware effect. note this bit is cleared on a sd card software reset (reg[6100h] bit 3 = 1). bit 7 sdwp status (read only) this bit indicates the status of sdwp (write protect) which is sampled by the clock referred to in table 10-75: ?sd memory card clock divide ratio selection,? on page 266 and table 10-76: ?system clock frequency and sd card clock,? on page 266 under reg[6100h] bits 7-4. when this bit returns a 0, sdwp is low input. when this bit returns a 1, sdwp is high input. bit 6 sdgpo inverted data this bit determines the polarity of sdgpo. when this bit = 0, sdgpo is forced high. when this bit = 1, sdgpo is forced low (default). bits 5-3 reserved the default value for these bits is 0. reg[6102h] sd memory card control register 1 default = 00x1h read/write n/a 15 14 13 12 11 10 9 8 sdwp status (ro) sdgpo inverted data reserved response data length multi block enable data bus width 7 6 5 4 3 2 1 0 free datasheet http:///
page 268 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 2 response data length this bit determines the length of the response from the memory card, in bits. this bit must be set for the appropriate length before initiating a receive response start (reg[6104h] bit 5). when this bit = 0, the response length is 48 bits (default) and sd memory card response registers a - f (reg[6134h] - reg[613eh] are used. when this bit = 1, the response length is 136 bits and sd memory card response regis- ters 0 - f (reg[6120h] - reg[613eh] are used. bit 1 multi block enable this bit controls the multi block read/write function. this bit must be set for the appropri- ate multi block setting before initiating a receive data start (reg[6104h] bit 3) or a send data start (reg[6104h] bit 2). when this bit = 0, multi block reads/writes are disabled (default). when this bit = 1, multi block reads/writes are enabled. bit 0 data bus width this bit specifies the sd memory card data bus width, in bits, and should be set according to the sd card. this bit must be set appropriately before initiating a receive data start (reg[6104h] bit 3) or a send data start (reg[6104h] bit 2). when this bit = 0, the data bus width is four bits and sddat[3:0] are used to transfer data. when this bit = 1, the data bus width is one bit and sddat0 is used to transfer data (default). bit 7 sdclk change start this bit controls changes to the sd memory card clock (sdclk) frequency. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the change to the sd memory card clock frequency begins for reads: when this bit returns a 0, the change to the sd memory card clock frequency has com- pleted. when this bit returns a 1, the change to the sd memory card clock frequency has not completed yet. the typical sequence for changing the sd memory card clock is as follows. 1. select the sdclk divide ratio using reg[6100h] bits 7-4. 2. write a 1 to the sdclk change start bit. 3. wait for the sdclk change start bit to return a 0. once this bit returns a 0, the change is effective and the interface can be enabled. reg[6104h] sd memory card function register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 sdclk change start send command start receive response start wait busy start receive data start send data start send 8 clock start synchronous reset start 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 269 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 6 send command start this bit controls the transmission of commands and parameters to the sd memory card. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the command/parameter stored in reg[610ch], reg[6110h] - reg[6116h] is transmitted on sdcmd. for reads: when this bit returns a 0, the command/parameter transmission has completed. when this bit returns a 1, the command/parameter is still being transmitted. bit 5 receive response start this bit controls the reception of responses from the sd memory card. the response data length bit (reg[6102h] bit 2) must be set according to the expected response length before starting to receive the response using this bit. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the response reception begins on sdcmd and can be read from reg[6120h] - reg[613eh]. for reads: when this bit returns a 0, the response reception has completed. when this bit returns a 1, the response reception is still being received. bit 4 wait busy start this bit controls the reception of wait busy signals from the sd memory card. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the wait busy reception begins. for reads: when this bit returns a 0, the wait busy reception has completed. when this bit returns a 1, the wait busy reception is still being received. bit 3 receive data start this bit controls the reception of data from the sd memory card. the response data length bit (reg[6102h] bit 2) and the multi block enable bit (reg[6102h] bit 1) must be set according to the expected response type before starting to receive the response. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the data reception begins on the sddat lines and is read from reg[6118h] - reg[611eh]. for reads: when this bit returns a 0, the data reception has completed. when this bit returns a 1, the data reception is still being received. free datasheet http:///
page 270 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 2 send data start this bit controls the transmission of data to the sd memory card. the multi block enable bit (reg[6102h] bit 1) must be set according to the type of data to be sent before starting to transmit the data. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the data written to reg[6110h] - reg[6116] is transmitted on the sddat lines. for reads: when this bit returns a 0, the data transmission has completed. when this bit returns a 1, the data transmission is still being sent. bit 1 send 8 clock start this bit controls the transmission of eight clocks to the sd memory card. for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the transmission begins. for reads: when this bit returns a 0, the transmission has completed. when this bit returns a 1, the eight clocks are still being transmitted. bit 0 synchronous reset start this bit performs a synchronous reset of the sd memory card interface. this reset has no effect on the following sd memory card registers (reg[6100h] - reg[6102h] and reg[6108h] - reg[613eh]). for writes: when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, a synchronous reset begins. for reads: when this bit returns a 0, the synchronous reset has completed. when this bit returns a 1, the synchronous reset is still taking place. note this register is read only and must not be written to at any time. bit 7 reserved the default value for this bit is 0. reg[6106h] sd memory card status register default = 00x0h read only n/a 15 14 13 12 11 10 9 8 reserved sdcd# status data writable data readable data crc error response over error response crc error time over error 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 271 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bit 6 sdcd# status (read only) this bit indicates the status of the sdcd# pin as taken with the sampling clock referred to in table 10-75: ?sd memory card clock divide ratio selection,? on page 266 and table 10-76: ?system clock frequency and sd card clock,? on page 266 under reg[6100h] bits 7-4. when this bit returns a 0, sdcd# is low input. when this bit returns a 1, sdcd# is high input. bit 5 data writable (read only) this bit indicates whether data can be written to the sd memory card. when this bit returns a 0, writing data is not possible. when this bit returns a 1, writing data is possible. bit 4 data readable (read only) this bit indicates whether data can be read from the sd memory card. when this bit returns a 0, reading data is not possible. when this bit returns a 1, reading data is possible. bit 3 data crc error (read only) this bit indicates when a data crc error has occurred. when this bit returns a 0, a crc error has not occurred. when this bit returns a 1, a crc error has occurred. bit 2 response over error (read only) this bit indicates that the response from the sd memory card has exceeded more than 64 clocks. when this bit returns a 0, the response is not more than 64 clocks. when this bit returns a 1, the response is more than 64 clocks. bit 1 response crc error (read only) this bit indicates that a crc error has occurred in the response from the sd memory card. when this bit returns a 0, a crc error has not occurred. when this bit returns a 1, a crc error has occurred. bit 0 time over error (read only) this bit indicates that a time over error has occurred during data transmission. when this bit returns a 0, a time over error has not occurred. when this bit returns a 1, a time over error has occurred. free datasheet http:///
page 272 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[6108h] bits 7-2 reserved the default value for these bits is 0. reg[6108h] bits 1-0 reg[610ah] bits 7-0 data length bits [9:0] these bits specify the sd memory card data length. the data length must be programmed such that the following formula is valid. 1 data length 512 bits 7-6 reserved the default value of these bits is 0. bits 5-0 command bits [5:0] these bits specify the command to be transmitted to the sdcmd signal when data is transmitted. bits 7-0 timer value bits [7:0] these bits specify the timer value used to limit the length of data and command accesses to/from the sd memory card. an error occurs when the timer value is exceeded by any sd memory card access. to determine the nature of the error, check the status bits in the sd memory card status register (reg[6106h]. timer limit = reg[610eh] bits 7-0 x sd memory card clock cycle (time) reg[6108h] sd memory card data length register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 reserved data length bits 9-8 7 6 5 4 3 2 1 0 reg[610ah] sd memory card data length register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 data length bits 7-0 7 6 5 4 3 2 1 0 reg[610ch] sd memory card command register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 reserved command bits 5-0 7 6 5 4 3 2 1 0 reg[610eh] sd memory card timer register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 timer value bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 273 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 7-0 parameter 0 bits [7:0] these bits specify parameter 0 which is used when data is transmitted to the sdcmd sig- nal. data is transmitted as follows: command, parameter 0, parameter 1, parameter 2, and parameter 3. bits 7-0 parameter 1 bits [7:0] these bits specify parameter 1 which is used when data is transmitted to the sdcmd sig- nal. data is transmitted as follows: command, parameter 0, parameter 1, parameter 2, and parameter 3. bits 7-0 parameter 2 bits [7:0] these bits specify parameter 2 which is used when data is transmitted to the sdcmd sig- nal. data is transmitted as follows: command, parameter 0, parameter 1, parameter 2, and parameter 3. bits 7-0 parameter 3 bits [7:0] these bits specify parameter 3 which is used when data is transmitted to the sdcmd sig- nal. data is transmitted as follows: command, parameter 0, parameter 1, parameter 2, and parameter 3. reg[6110h] sd memory card parameter register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 parameter 0 bits 7-0 7 6 5 4 3 2 1 0 reg[6112h] sd memory card parameter register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 parameter 1 bits 7-0 7 6 5 4 3 2 1 0 reg[6114h] sd memory card parameter register 2 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 parameter 2 bits 7-0 7 6 5 4 3 2 1 0 reg[6116h] sd memory card parameter register 3 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 parameter 3 bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
page 274 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[6118h] bits 7-0 reg[611ah] bits 7-0 reg[611ch] bits 7-0 reg[611eh] bits 7-0 write data / read data these bits specify the r ead/write data to be received from/tr ansmitted to the sd memory card. when the data writable bit returns a 0 (reg[6106h] bit 5 = 0), writing data to the sd memory card is not possible. when the data readable bit returns a 0 (reg[6106h] bit 4 = 0), reading data from the sd memory card is not possible. note these registers are write only unless data has been received from the sdcard. bits 7-0 response 0 bits [7:0] these bits contain the response 0 data received from the sd memory card at the sdcmd signal. bits 7-0 response 1 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 1 data received from the sd memory card at the sdcmd signal. reg[6118h~611eh] sd memory card data register default = 00xxh read/write n/a 15 14 13 12 11 10 9 8 write data / read data 7 6 5 4 3 2 1 0 reg[6120h] sd memory card response register 0 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 0 bits 7-0 7 6 5 4 3 2 1 0 reg[6122h] sd memory card response register 1 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 1 bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 275 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 7-0 response 2 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 2 data received from the sd memory card at the sdcmd signal. bits 7-0 response 3 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 3 data received from the sd memory card at the sdcmd signal. bits 7-0 response 4 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 4 data received from the sd memory card at the sdcmd signal. bits 7-0 response 5 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 5 data received from the sd memory card at the sdcmd signal. reg[6124h] sd memory card response register 2 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 2 bits 7-0 7 6 5 4 3 2 1 0 reg[6126h] sd memory card response register 3 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 3 bits 7-0 7 6 5 4 3 2 1 0 reg[6128h] sd memory card response register 4 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 4 bits 7-0 7 6 5 4 3 2 1 0 reg[612ah] sd memory card response register 5 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 5 bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
page 276 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 7-0 response 6 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 6 data received from the sd memory card at the sdcmd signal. bits 7-0 response 7 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 7 data received from the sd memory card at the sdcmd signal. bits 7-0 response 8 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 8 data received from the sd memory card at the sdcmd signal. bits 7-0 response 9 bits [7:0] these bits are used only when the response data length is 136 bits (reg[6102h] bit 2 = 1). these bits contain the response 9 data received from the sd memory card at the sdcmd signal. reg[612ch] sd memory card response register 6 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 6 bits 7-0 7 6 5 4 3 2 1 0 reg[612eh] sd memory card response register 7 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 7 bits 7-0 7 6 5 4 3 2 1 0 reg[6130h] sd memory card response register 8 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 8 bits 7-0 7 6 5 4 3 2 1 0 reg[6132h] sd memory card response register 9 default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response 9 bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 277 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 7-0 response a bits [7:0] these bits contain the response a data received from the sd memory card at the sdcmd signal. bits 7-0 response b bits [7:0] these bits contain the response b data received from the sd memory card at the sdcmd signal. its 7-0 response c bits [7:0] these bits contain the response c data received from the sd memory card at the sdcmd signal. bits 7-0 response d bits [7:0] these bits contain the response d data received from the sd memory card at the sdcmd signal. reg[6134h] sd memory card response register a default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response a bits 7-0 7 6 5 4 3 2 1 0 reg[6136h] sd memory card response register b default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response b bits 7-0 7 6 5 4 3 2 1 0 reg[6138h] sd memory card response register c default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response c bits 7-0 7 6 5 4 3 2 1 0 reg[613ah] sd memory card response register d default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response d bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
page 278 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 7-0 response e bits [7:0] these bits contain the response e data received from the sd memory card at the sdcmd signal. bits 7-0 response f bits [7:0] these bits contain the response f data received from the sd memory card at the sdcmd signal. reg[613ch] sd memory card response register e default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response e bits 7-0 7 6 5 4 3 2 1 0 reg[613eh] sd memory card response register f default = 00ffh read only n/a 15 14 13 12 11 10 9 8 response f bits 7-0 7 6 5 4 3 2 1 0 free datasheet http:///
epson research and development page 279 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 10.4.21 2d bitblt registers bit 7 bitblt reset (write only) when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the 2d bitblt engine is reset. bit 0 bitblt enable (write only) when a 0 is written to this bit, the 2d bitblt operation is terminated. when a 1 is written to this bit, the 2d bitblt operation is started. bits 15-8 reserved the default value for these bits is 0. bit 2 bitblt color format select this bit selects the color format that the 2d operation is applied to. when this bit = 0, 8 bpp (256 color) format is selected. when this bit = 1, 16 bpp (64k color) format is selected. bit 1 bitblt destination linear select when this bit = 0, the destination bitblt is stored as a rectangular region of memory. the bitblt memory address offset register (reg[8014h]) determines the address offset from the start of one line to the next line. when this bit = 1, the destination bitblt is stored as a contiguous linear block of memory. bit 0 bitblt source linear select when this bit = 0, the source bitblt is stored as a rectangular region of memory. the bitblt memory address offset register (reg[8014h]) determines the address offset from the start of one line to the next line. when this bit = 1, the source bitblt is stored as a contiguous linear block of memory. reg[8000h] bitblt control register 0 default = 0000h write only n/a 15 14 13 12 11 10 9 8 bitblt reset n/a bitblt enable 7 6 5 4 3 2 10 reg[8002h] bitblt control register 1 default = 0000h read/write reserved 15 14 13 12 11 10 9 8 n/a color format select dest linear select source linear select 7 6 5 4 3210 free datasheet http:///
page 280 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 12-7 reserved the default value for these bits is 0. bit 6 bitblt fifo not-empty status (read only) this bit indicates if the bitblt fifo is empty or not. when this bit = 0, the bitblt fifo is empty. when this bit = 1, the bitblt fifo has at least one entry. to reduce system memory read latency, software can monitor this bit prior to a bitblt read burst operation. the following table shows the number of words available in the bitblt fifo under different status conditions. bit 5 bitblt fifo half full status (read only) this bit indicates whether the bitblt fifo is more or less than half full. when this bit = 0, the bitblt fifo is less than half full. when this bit = 1, the bitblt fifo is half full or greater than half full. bit 4 bitblt fifo full status (read only) this bit indicates whether the bitblt fifo is full or not. this bit must be confirmed as not full (0) before writing to the bitblt fifo. when this bit = 0, the bitblt fifo is not full. when this bit = 1, the bitblt fifo is full. bit 0 bitblt busy status (read only) this bit indicates the state of the current bitblt operation. when this bit = 0, the bitblt operation is complete. when this bit = 1, the bitblt operation is in progress. reg[8006h] is reserved this register is reserved and should not be written. reg[8004h] bitblt status register 0 default = 0000h read only n/a reserved 15 14 13 12 11 10 9 8 reserved fifo not empty fifo half full fifo full status n/a bitblt busy status 7654 3 2 10 table 10-77: possible bitblt fifo writes bitblt status register (reg[8004h]) word writes available fifo not empty status fifo half full status fifo full status 00 016 10 08 11 0up to 8 1 1 1 0 (do not write) free datasheet http:///
epson research and development page 281 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 3-0 bitblt operation bits [3:0] these bits specify the 2d operation to be performed. reg[8008h] bitblt command register 0 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a bitblt operation bits 3-0 7 6 5 43210 table 10-78: bitblt operation selection bitblt operation bits [3:0] bitblt operation 0000b reserved 0001b read bitblt 0010b move bitblt in positive direction with rop 0011b move bitblt in negative direction with rop 0100b reserved 0101b transparent move bitblt in positive direction 0110b pattern fill with rop 0111b pattern fill with transparency 1000b reserved 1001b reserved 1010b move bitblt with color expansion 1011b move bitblt with color expansion and transparency 1100b solid fill other combinations reserved free datasheet http:///
page 282 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bits 3-0 bitblt raster operation code/color expansion bits [3:0] these bits determine the rop code for write bitblt and move bitblt. bits 2-0 also specify the start bit position for color expansion. note s = source, d = destination, p = pattern. reg[800ah] bitblt command register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a bitblt rop code bits 3-0 7 6 5 43210 table 10-79: bitblt rop code/color expansion function selection bitblt rop code bits [3:0] boolean function for write bitblt and move bitblt boolean function for pattern fill start bit position for color expansion 0000b 0 (blackness) 0 (blackness) bit 0 0001b ~s . ~d or ~(s + d) ~p . ~d or ~(p + d) bit 1 0010b ~s . d ~p . d bit 2 0011b ~s ~p bit 3 0100b s . ~d p . ~d bit 4 0101b ~d ~d bit 5 0110b s ^ d p ^ d bit 6 0111b ~s + ~d or ~(s . d) ~p + ~d or ~(p . d) bit 7 1000b s . d p . d bit 0 1001b ~(s ^ d) ~(p ^ d) bit 1 1010b d d bit 2 1011b ~s + d ~p + d bit 3 1100b s p bit 4 1101b s + ~d p + ~d bit 5 1110b s + d p + d bit 6 1111b 1 (whiteness) 1 (whiteness) bit 7 free datasheet http:///
epson research and development page 283 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential reg[800eh] bits 2-0 reg[800ch] bits 15-0 bitblt source start address bits [18:0] these bits specify the source start address for the bitblt operation. if data is sourced from the cpu, then bit 0 is used for byte alignment within a 16-bit word and the other address bits are ignored. in pattern fill operation, the bitblt source start address is defined by the following equation. value programmed to the source start address register = pattern base address + pattern line offset + pixel offset. the following table shows how source start address register is defined for 8 and 16 bpp color depths. reg[800eh] bits 4-3 reserved the default value for these bits is 0. reg[800ch] bitblt source start address register 0 default = 0000h read/write bitblt source start address bits 15-8 15 14 13 12 11 10 9 8 bitblt source start address bits 7-0 76543210 reg[800eh] bitblt source start address register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 reserved bitblt source start address bits 18-16 7 6 543210 table 10-80: bitblt source start address selection color format pattern base address[18:0] pa ttern line offset[2:0] pixel offset[3:0] 8 bpp bitblt source start address[18:6] bitblt source start address[5:3] bitblt source start address[2:0] 16 bpp bitblt source start address[18:7] bitblt source start address[6:4] bitblt source start address[3:0] free datasheet http:///
page 284 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential reg[8012h] bits 4-0 reg[8010h] bits 15-0 bitblt destination start address bits [18:0] these bits specify the destination start address for the bitblt operation. reg[8012h] bits 4-3 reserved the default value for these bits is 0. bits 10-0 bitblt memory address offset bits [10:0] these bits are the display?s 11-bit address offset from the starting word of line n to the starting word of line n + 1 . they are used only for address calculation when the bitblt is configured as a rectangular region of memory. they are not used for the displays. bits 9-0 bitblt width bits [9:0] these bits determine the bitblt width in pixels. bitblt width in pixels = (reg[8018h] bits 9-0) + 1 reg[8010h] bitblt destination start address register 0 default = 0000h read/write bitblt destination start address bits 15-8 15 14 13 12 11 10 9 8 bitblt destination start address bits 7-0 76543210 reg[8012h] bitblt destination start address register 1 default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a reserved bitblt destination start address bits 18-16 7 6 543210 reg[8014h] bitblt memory address offset register default = 0000h read/write n/a bitblt memory address offset bits 10-8 15 14 13 12 11 10 9 8 bitblt memory address offset bits 7-0 76543210 reg[8018h] bitblt width register default = 0000h read/write n/a bitblt width bits 9-8 15 14 13 12 11 10 9 8 bitblt width bits 7-0 76543210 free datasheet http:///
epson research and development page 285 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential bits 9-0 bitblt height bits [9:0] these bits determine the bitblt height in lines. bitblt height in lines = (reg[801ch] bits 9-0) + 1 bits 15-0 bitblt background color bits [15:0] these bits specify the bitblt background color for color expansion or key color for transparent bitblt. for 16 bpp color depths (reg[8000h] bit 18 = 1), bits 15-0 are used. for 8 bpp color depths (reg[8000h] bit 18 = 0), bits 7-0 are used. bits 15-0 bitblt foreground color bits [15:0] these bits specify the bitblt foreground color for color expansion or solid fill. for 16 bpp color depths (reg[8000h] bit 18 = 1), bits 15-0 are used. for 8 bpp color depths (reg[8000h] bit 18 = 0), bits 7-0 are used. bit 0 bitblt operation complete flag this bit is set when the bitblt operation is finished. this bit is masked by reg[8032h] bit 0. when a 0 is written to this bit, there is no hardware effect. when a 1 is written to this bit, the flag is cleared. reg[801ch] bitblt height register default = 0000h read/write n/a bitblt height bits 9-8 15 14 13 12 11 10 9 8 bitblt height bits 7-0 76543210 reg[8020h] bitblt background color register default = 0000h read/write bitblt background color bits 15-8 15 14 13 12 11 10 9 8 bitblt background color bits 7-0 76543210 reg[8024h] bitblt foreground color register default = 0000h read/write bitblt foreground color bits 15-8 15 14 13 12 11 10 9 8 bitblt foreground color bits 7-0 76543210 reg[8030h] bitblt interrupt status register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a bitblt operation complete flag 7 6 5 4 3 2 10 free datasheet http:///
page 286 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential bit 0 bitblt operation complete interrupt enable this bit determines whether an interrupt is generated when the current bitblt operation finishes. when this bit = 0, the interrupt is disabled. when this bit = 1, the interrupt is enabled. bits 15-0 bitblt data bits [15:0] this register specifies the bitblt data when a direct interface is selected (cnf[4:2]). when an indirect interface is selected, bitblt data must be specified using the indirect interface 2d bitblt data read/write port register (reg[002ah]). reg[8032h] bitblt interrupt control register default = 0000h read/write n/a 15 14 13 12 11 10 9 8 n/a bitblt operation complete interrupt enable 7 6 5 4 3 2 10 reg[10000h] 2d bitblt data memory mapped region register default = not applicable read/write bitblt data bits 15-8 15 14 13 12 11 10 9 8 bitblt data bits 7-0 76543210 free datasheet http:///
epson research and development page 287 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 11 power save modes 11.1 power-on/power-off sequence figure 11-1: power-on/power-off sequence power-on hardware reset pll bypass mode pll set power save mode disable system clock set 1. core v dd 2. pll v dd 3. hiov dd , piov dd , ciov dd , siov dd reset pulse > 1 clki period pll power down disable reg[000eh] bits 15-0 reg[0010h] bits 15-12 reg[0012h] bit 0 = 0 reg[0018h] bits 1-0 reg[0014h] bit 0 = 0 registers initialize check memory status normal mode reg[0014h] bit 6 power save mode enable reg[0014h] bit 0 = 1 1. hiov dd , piov dd , ciov dd , siov dd 2. pll v dd 3. core v dd pll power down enable reg[0012h] bit 0 = 1 power-off pll bypass mode power-off sequence power-on sequence (see note) note: there may be up to a 100ms delay before the pll output becomes stable. the S1D13717 must not be accessed during this time. reg[0016h] clki input is required software reset free datasheet http:///
page 288 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 11-2: power modes power save mode invalid (pll bypass) reg[0014h] bit 0 = 0 pll power down invalid reg[0012h] bit 0 = 0 power save mode valid reg[0014h] bit 0 = 1 pll power down valid reg[0012h] bit 0 = 1 power save mode power save mode invalid reg[0014h] bit 0 = 0 power save mode valid (pll bypass) reg[0014h] bit 0 = 1 power-off standby mode normal mode power-on external clock mode hardware reset software reset free datasheet http:///
epson research and development page 289 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 11.1.1 power-on when powering-on the S1D13717, the following sequence must be used unless all power is active within 10 ms. 1. corev dd on 2. pllv dd on 3. hiov dd , piov dd , siov dd , ciov dd on 11.1.2 reset after power-on, an active low hardware reset pulse, which is one external clock cycle (clki) in length, must be input to the s1d13715 reset# pin. all registers, including the clock setting registers (reg[000eh]-[0018h]) are reset by a hardware reset. after releasing the reset# signal, the clock setting registers are immediately accessible. a software reset is enabled by writing to reg[0016h]. all registers above reg[0018h] are reset to the default values by a software reset (reg[0000h] - [0018h] are not reset). the following conditions apply to software reset. ? after initialization, and before the software reset (reg[0016h]), power save mode should be enabled (reg[0014h] bit 0 = 1). ? after the software reset, power save mode can be disabled (reg[0016h] bit 0 = 0) after waiting 100ms. all registers, synchronous and asynchronous, may now be accessed. 11.1.3 standby mode standby mode offers the lowest power consumption because all internal clock supplies are stopped and the pll is disabled. this mode must be entered before turning off the power supplies or setting the pll registers. in order to switch to the standby mode, a pll power down should be executed (reg[0012h] bit 0 = 1). after power down, the clki input should be continued for a minimum 100us to allow the pll power down to complete. 11.1.4 power save mode power save mode stops all internal clock supplies. this mode must be entered before setting the system clock setting register (reg[0018h]). also, there may be up to a 100ms delay before the pll output becomes stable after it is enabled. the s1d1717 should be in power save mode during this time. free datasheet http:///
page 290 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 11.1.5 normal mode all functions are available in normal mode. however, clocks to modules that are not in use are dynamically stopped. before enabling power save mode (reg[0014] bit 0 = 1) from normal mode, confirm that the memory controller is idle (reg[0014h] bit 6 = 1). 11.1.6 power-off when powering-off the S1D13717, the following sequence must be used. 1. hiov dd , piov dd , siov dd , ciov dd off 2. pllv dd off 3. corev dd off 11.2 power save mode function table 11-1: power save mode function selection item reset state power save mode normal mode io (register) access possible? reg[0000h-0018h], reg[0300h-030eh] yes yes yes all other registers no no yes memory access possible? no no yes look-up table registers access possible? no no yes display active? no no yes lcd1, lcd2 interface outputs and gpio pins configured for panel support fpcs1# inactive inactive active all other pins forced low forced low active gpio pins configured as gpios cnf2 = 1 input gpio state gpio state cnf2 = 0 forced low gpo state gpo state camera interface pins forced low forced low active system clock forced low active active pixel clock forced low forced low active serial clock for the lcd2 serial panel i/f setting (reg[0032h] bits 1-0 = 00b or 10b) inactive active active for all other settings forced low forced low active camera clock forced low forced low active jpeg module reg[0980] bit 0 = 0 inactive inactive inactive reg[0980] bit 0 = 1 inactive inactive active bitblt module inactive inactive active sd card interface reg[6000] bit 0 = 0 inactive inactive inactive reg[6000] bit 0 = 1 inactive inactive active free datasheet http:///
epson research and development page 291 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 12 lut architecture 12.1 lut1 (main window) for 8 bpp figure 12-1: lut1 (main window) for 8 bpp architecture red look-up table 256x8 reg[0400h] bits 7-0 reg[0404h] bits 7-0 reg[0408h] bits 7-0 reg[040ch] bits 7-0 0000 0000 0000 0001 8-bit-per-pixel data 8-bit red data from display buffer 0000 0010 0000 0011 reg[0410h] bits 7-0 reg[0414h] bits 7-0 reg[0418h] bits 7-0 reg[041ch] bits 7-0 0000 0100 0000 0101 0000 0110 0000 0111 reg[07e0h] bits 7-0 reg[07e4h] bits 7-0 reg[07e8h] bits 7-0 reg[07ech] bits 7-0 reg[07f0h] bits 7-0 reg[07f4h] bits 7-0 reg[07f8h] bits 7-0 reg[07fch] bits 7-0 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 8-bit green data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 8-bit blue data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 green look-up table 256x8 reg[0400h] bits 15-8 reg[0404h] bits 15-8 reg[0408h] bits 15-8 reg[040ch] bits 15-8 reg[0410h] bits 15-8 reg[0414h] bits 15-8 reg[0418h] bits 15-8 reg[041ch] bits 15-8 reg[07e0h] bits 15-8 reg[07e4h] bits 15-8 reg[07e8h] bits 15-8 reg[07ech] bits 15-8 reg[07f0h] bits 15-8 reg[07f4h] bits 15-8 reg[07f8h] bits 15-8 reg[07fch] bits 15-8 blue look-up table 256x8 reg[0402h] bits 7-0 reg[0406h] bits 7-0 reg[040ah] bits 7-0 reg[040eh] bits 7-0 reg[0412h] bits 7-0 reg[0416h] bits 7-0 reg[041ah] bits 7-0 reg[041eh] bits 7-0 reg[07e2h] bits 7-0 reg[07e6h] bits 7-0 reg[07eah] bits 7-0 reg[07eeh] bits 7-0 reg[07f2h] bits 7-0 reg[07f6h] bits 7-0 reg[07fah] bits 7-0 reg[07feh] bits 7-0 free datasheet http:///
page 292 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 12.2 lut2 (pip + window) for 8 bpp architecture figure 12-2: lut2 (pip + window) for 8 bpp architecture red look-up table 8x8 reg[0800h] bits 7-0 reg[0804h] bits 7-0 reg[0808h] bits 7-0 reg[080ah] bits 7-0 000 001 3-bit red data 8-bit red data from display buffer 010 011 reg[0810h] bits 7-0 reg[0814h] bits 7-0 reg[0818h] bits 7-0 reg[081ah] bits 7-0 100 101 110 111 000 001 8-bit green data 010 011 100 101 110 111 8-bit blue data green look-up table 8x8 blue look-up table 4x8 00 01 10 11 reg[0802h] bits 7-0 reg[0806h] bits 7-0 reg[080ah] bits 7-0 reg[080eh] bits 7-0 3-bit green data 2-bit blue data from display buffer from display buffer reg[0800h] bits 15-8 reg[0804h] bits 15-8 reg[0808h] bits 15-8 reg[080ah] bits 15-8 reg[0810h] bits 15-8 reg[0814h] bits 15-8 reg[0818h] bits 15-8 reg[081ah] bits 15-8 free datasheet http:///
epson research and development page 293 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 12.3 lut1 (main window) for 16 bpp architecture figure 12-3: lut1 (main window) for 16 bpp architecture red look-up table 32x8 00000 00001 5-bit red data 8-bit red data from display buffer 00010 00011 00100 00101 00110 00111 11000 11001 11010 11011 11100 11101 11110 11111 000000 000001 8-bit green data 000010 000011 000100 000101 000110 000111 8-bit blue data green look-up table 64x8 blue look-up table 32x8 111000 111001 111010 111011 111100 111101 111110 111111 00000 00001 00010 00011 00100 00101 00110 00111 11000 11001 11010 11011 11100 11101 11110 11111 6-bit green data 5-bit blue data from display buffer from display buffer reg[0400h] bits 7-0 reg[0404h] bits 7-0 reg[0408h] bits 7-0 reg[040ch] bits 7-0 reg[0410h] bits 7-0 reg[0414h] bits 7-0 reg[0418h] bits 7-0 reg[041ch] bits 7-0 reg[0470h] bits 7-0 reg[0474h] bits 7-0 reg[0478h] bits 7-0 reg[047ch] bits 7-0 reg[0470h] bits 7-0 reg[0474h] bits 7-0 reg[0478h] bits 7-0 reg[047ch] bits 7-0 reg[0400h] bits 15-8 reg[0404h] bits 15-8 reg[0408h] bits 15-8 reg[040ch] bits 15-8 reg[0410h] bits 15-8 reg[0414h] bits 15-8 reg[0418h] bits 15-8 reg[041ch] bits 15-8 reg[04e0h] bits 15-8 reg[04e4h] bits 15-8 reg[04e8h] bits 15-8 reg[04ech] bits 15-8 reg[04f0h] bits 15-8 reg[04f4h] bits 15-8 reg[04f8h] bits 15-8 reg[04fch] bits 15-8 reg[0402h] bits 7-0 reg[0406h] bits 7-0 reg[040ah] bits 7-0 reg[040eh] bits 7-0 reg[0412h] bits 7-0 reg[0416h] bits 7-0 reg[041ah] bits 7-0 reg[041eh] bits 7-0 reg[0472h] bits 7-0 reg[0476h] bits 7-0 reg[047ah] bits 7-0 reg[047eh] bits 7-0 reg[0472h] bits 7-0 reg[0476h] bits 7-0 reg[047ah] bits 7-0 reg[047eh] bits 7-0 free datasheet http:///
page 294 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 12.4 lut2 (pip + window) for 16 bpp architecture figure 12-4: lut2 (pip + window) for 16 bpp architecture red look-up table 32x8 00000 00001 5-bit red data 8-bit red data from display buffer 00010 00011 00100 00101 00110 00111 11000 11001 11010 11011 11100 11101 11110 11111 000000 000001 8-bit green data 000010 000011 000100 000101 000110 000111 8-bit blue data green look-up table 64x8 blue look-up table 32x8 111000 111001 111010 111011 111100 111101 111110 111111 00000 00001 00010 00011 00100 00101 00110 00111 11000 11001 11010 11011 11100 11101 11110 11111 6-bit green data 5-bit blue data from display buffer from display buffer reg[0800h] bits 7-0 reg[0804h] bits 7-0 reg[0808h] bits 7-0 reg[080ch] bits 7-0 reg[0810h] bits 7-0 reg[0814h] bits 7-0 reg[0818h] bits 7-0 reg[081ch] bits 7-0 reg[0870h] bits 7-0 reg[0874h] bits 7-0 reg[0878h] bits 7-0 reg[087ch] bits 7-0 reg[0870h] bits 7-0 reg[0874h] bits 7-0 reg[0878h] bits 7-0 reg[087ch] bits 7-0 reg[0800h] bits 15-8 reg[0804h] bits 15-8 reg[0808h] bits 15-8 reg[080ch] bits 15-8 reg[0810h] bits 15-8 reg[0814h] bits 15-8 reg[0818h] bits 15-8 reg[081ch] bits 15-8 reg[08e0h] bits 15-8 reg[08e4h] bits 15-8 reg[08e8h] bits 15-8 reg[08ech] bits 15-8 reg[08f0h] bits 15-8 reg[08f4h] bits 15-8 reg[08f8h] bits 15-8 reg[08fch] bits 15-8 reg[0802h] bits 7-0 reg[0806h] bits 7-0 reg[080ah] bits 7-0 reg[080eh] bits 7-0 reg[0812h] bits 7-0 reg[0816h] bits 7-0 reg[081ah] bits 7-0 reg[081eh] bits 7-0 reg[0872h] bits 7-0 reg[0876h] bits 7-0 reg[087ah] bits 7-0 reg[087eh] bits 7-0 reg[0872h] bits 7-0 reg[0876h] bits 7-0 reg[087ah] bits 7-0 reg[087eh] bits 7-0 free datasheet http:///
epson research and development page 295 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13 display data formats 13.1 display data for lut mode 13.1.1 8 bpp mode figure 13-1: lut1 for 8 bpp mode figure 13-2: lut2 for 8 bpp mode host address display buffer bit 7 bit 0 panel display p 0 p 1 p 2 (a n , b n , c n , d n , e n , f n , g n , h n ) lut1 p n = rgb value from lut index a 0 b 0 c 0 d 0 e 0 f 0 g 0 h 0 a 1 b 1 c 1 d 1 e 1 f 1 g 1 h 1 a 2 b 2 c 2 d 2 e 2 f 2 g 2 h 2 byte 0 byte 1 byte 2 host address panel display lut2 (r n 7 , r n 6 , r n 5 ) (g n 7 , g n 6 , g n 5 ) (b n 7 , b n 6 ) byte 0 byte 1 byte 2 byte 3 p 0 p 1 p n = rgb value from lut index display buffer bit 7 bit 0 g 0 2 r 0 2 r 0 1 g 0 1 g 0 0 r 0 0 b 0 0 b 0 1 g 1 2 r 1 2 r 1 1 g 1 1 g 1 0 r 1 0 b 1 0 b 1 1 g 2 2 r 2 2 r 2 1 g 2 1 g 2 0 r 2 0 b 2 0 b 2 1 free datasheet http:///
page 296 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.1.2 16 bpp mode figure 13-3: lut1 for 16 bpp mode figure 13-4: lut2 for 16 bpp mode host address bit 7 bit 0 g 0 5 r 0 4 r 0 3 r 0 2 r 0 1 panel display (r n 4 , r n 3 , r n 2 , r n 1 , r n 0 ) (g n 5 ,g n 4 , g n 3 , g n 2 , g n 1 , g n 0 ) (b n 4 , b n 3 , b n 2 , b n 1 , b n 0 ) byte 0 byte 1 byte 2 byte 3 g 0 4 g 0 3 g 0 2 g 0 1 g 0 0 b 0 4 b 0 3 b 0 2 b 0 1 b 0 0 r 0 0 g 1 5 r 1 4 r 1 3 r 1 2 r 1 1 g 1 4 g 1 3 g 1 2 g 1 1 g 1 0 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 r 1 0 p 0 p 1 p n = rgb value from lut index display buffer lut1 host address bit 7 bit 0 g 0 5 r 0 4 r 0 3 r 0 2 r 0 1 panel display (r n 4 , r n 3 , r n 2 , r n 1 , r n 0 ) (g n 5 ,g n 4 , g n 3 , g n 2 , g n 1 , g n 0 ) (b n 4 , b n 3 , b n 2 , b n 1 , b n 0 ) byte 0 byte 1 byte 2 byte 3 g 0 4 g 0 3 g 0 2 g 0 1 g 0 0 b 0 4 b 0 3 b 0 2 b 0 1 b 0 0 r 0 0 g 1 5 r 1 4 r 1 3 r 1 2 r 1 1 g 1 4 g 1 3 g 1 2 g 1 1 g 1 0 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 r 1 0 p 0 p 1 p n = rgb value from lut index display buffer lut2 free datasheet http:///
epson research and development page 297 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.2 display data for lut bypass mode 13.2.1 8 bpp mode figure 13-5: lut bypass for 8 bpp mode 13.2.2 16 bpp mode figure 13-6: lut bypass for 16 bpp mode host address display memory bit 7 bit 0 r 0 2 r 0 1 r 0 0 g 0 2 g 0 1 g 0 0 b 0 1 b 0 0 byte 0 byte 1 byte 2 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 r 1 2 r 1 1 r 1 0 g 1 2 g 1 1 g 1 0 b 1 1 b 1 0 r 2 2 r 2 1 r 2 0 g 2 2 g 2 1 g 2 0 b 2 1 b 2 0 p n = (r n 2-0 , g n 2-0 , b n 1-0 ) 3-3-2 rgb r 0 4 host address display buffer bit 7 bit 0 r 0 3 r 0 2 r 0 1 r 0 0 g 0 5 g 0 4 g 0 3 g 0 2 g 0 1 g 0 0 b 0 4 b 0 3 b 0 2 b 0 1 b 0 0 r 1 4 r 1 3 r 1 2 r 1 1 r 1 0 g 1 5 g 1 4 g 1 3 g 1 2 g 1 1 g 1 0 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 5-6-5 rgb byte 0 byte 1 byte 2 byte 3 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = (r n 4-0 , g n 5-0 , b n 4-0 ) free datasheet http:///
page 298 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.3 display data flow the 8 bpp or 16 bpp data in the display buffer is expanded to 24 bpp (rgb=8:8:8) either by the internal lut or by bit cover (see section 13.3.2, ?bit cover when lut bypassed? on page 298). before being output, the lcd data is altered depending on the specified lcd panel data format. for more information, see section 5.5, ?lcd interface pin mapping? on page 46 , section 13.4, ?parallel data format? on page 299 and section 13.5, ?serial data format? on page 305 . 13.3.1 display buffer data display data can be stored in the display buffer as either 8 bpp or 16 bpp. data from the camera interface or jpeg decoder must be stored as 16 bpp only. the data format for each color depth differs based on whether the lut is used or the lut is bypassed. 13.3.2 bit cover when lut bypassed when the lut is bypassed, 8 bpp and 16 bpp data are not indexed using the lut. the data is expanded to 24 bpp (or bit covered) by copying the msb to the lsbs as follows. figure 13-7: data bit cover when the lut is bypassed 13.3.3 overlay the overlay function compares 24-bit data after the lut. if the 24-bit data is the same as the overlay key color (see reg[0204h] - reg[0208h], reg[0304h] - reg[0326h]), the data that will be output is the pip+ window data instead of the main window data. for more information on the overlay function, see section 15.1, ?overlay display? on page 316. 8 bpp memory data 16 bpp memory data r g b r g b r0 r2 r1 g2 g1 g0 b1 b0 r0 r2 r1 g2 g1 g0 b1 b0 r4 r3 g5 g4 g3 b4 b3 b2 internal 24 bpp data (lut bypass mode) r0 r2 r1 g2 g1 g0 b1 b0 r4 r3 g5 g4 g3 b4 b3 b2 r4 b4 r0 r2 r1 g2 g1 g0 b1 b0 r2 r2 r2 g2 g2 g2 b1 b1 b1 b1 r g b r g b b1 b1 g2 g2 r2 r2 b4 b4 g5 g5 r4 r4 free datasheet http:///
epson research and development page 299 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.4 parallel data format when the panel interface bits are set for a parallel panel(s) (reg[0032h] bits 1-0 = 01b or 10b or 11b), a parallel data format must be selected. reg[0056h] bits 2-0 select the data format for lcd1 and reg[005eh] bits 2-0 select the data format for lcd2. note when reg[0032h] bits 1-0 = 10b, mode 2 is enabled and only lcd1 is configured as a parallel panel. when reg[0032h] bits 1-0 = 11b, mode 3 is enabled and both lcd1 and lcd2 are configured as parallel panels. when reg[0032h] bits 1-0 = 01b, mode 4 is enabled and only lcd2 is configured as a parallel panel. for more information on possible panel combinations, see reg[0032h] bits 1-0 in section 10.4.4, ?lcd panel interface generic setting registers? on page 134. 13.4.1 8-bit parallel, rgb=3:3:2 when reg[0056h] bits 2-0 = 000b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 000b, the lcd2 data format is specified as this format. table 13-1: 8-bit parallel, rgb=3:2:2 data format selection cycle count 1 2 3 ... n+1 d7 r 0 5 r 1 5 r 2 5 ... r n 5 d6 r 0 4 r 1 4 r 2 4 ... r n 4 d5 r 0 3 r 1 3 r 2 3 ... r n 3 d4 g 0 5 g 1 5 g 2 5 ... g n 5 d3 g 0 4 g 1 4 g 2 4 ... g n 4 d2 g 0 3 g 1 3 g 2 3 ... g n 3 d1 b 0 5 b 1 5 b 2 5 ... b n 5 d0 b 0 4 b 1 4 b 2 4 ... b n 4 free datasheet http:///
page 300 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.4.2 8-bit parallel, rgb=4:4:4 when reg[0056h] bits 2-0 = 001b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 001b, the lcd2 data format is specified as this format. 13.4.3 8-bit parallel, rgb=8:8:8 when reg[0056h] bits 2-0 = 011b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 011b, the lcd2 data format is specified as this format. table 13-2: 8-bit parallel, rgb=4:4:4 data format selection cycle count 1 2 3 ... 3n+1 3n+2 3n+3 d7 r 0 5 b 0 5 g 1 5 ... r n 5 b n 5 g n+1 5 d6 r 0 4 b 0 4 g 1 4 ... r n 4 b n 4 g n+1 4 d5 r 0 3 b 0 3 g 1 3 ... r n 3 b n 3 g n+1 3 d4 r 0 2 b 0 2 g 1 2 ... r n 2 b n 2 g n+1 2 d3 g 0 5 r 1 5 b 1 5 ... g n 5 r n+1 5 b n+1 5 d2 g 0 4 r 1 4 b 1 4 ... g n 4 r n+1 4 b n+1 4 d1 g 0 3 r 1 3 b 1 3 ... g n 3 r n+1 3 b n+1 3 d0 g 0 2 r 1 2 b 1 2 ... g n 2 r n+1 2 b n+1 2 table 13-3: 8-bit parallel, rgb=8:8:8 data format selection cycle count 1 2 3 ... 3n+1 3n+2 3n+3 d7 r 0 7 g 0 7 b 0 7 ... r n 7 g n 7 b n 7 d6 r 0 6 g 0 6 b 0 6 ... r n 6 g n 6 b n 6 d5 r 0 5 g 0 5 b 0 5 ... r n 5 g n 5 b n 5 d4 r 0 4 g 0 4 b 0 4 ... r n 4 g n 4 b n 4 d3 r 0 3 g 0 3 b 0 3 ... r n 3 g n 3 b n 3 d2 r 0 2 g 0 2 b 0 2 ... r n 2 g n 2 b n 2 d1 r 0 1 g 0 1 b 0 1 ... r n 1 g n 1 b n 1 d0 r 0 0 g 0 0 b 0 0 ... r n 0 g n 0 b n 0 free datasheet http:///
epson research and development page 301 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.4.4 16-bit parallel, rgb=4:4:4 when reg[0056h] bits 2-0 = 101b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 101b, the lcd2 data format is specified as this format. table 13-4: 16-bit parallel, rgb=4:4:4 data format selection cycle count 1 2 3 ... n+1 d15 r 0 5 r 1 5 r 2 5 ... r n 5 d14 r 0 4 r 1 4 r 2 4 ... r n 4 d13 r 0 3 r 1 3 r 2 3 ... r n 3 d12 r 0 2 r 1 2 r 2 2 ... r n 2 d11 g 0 5 g 1 5 g 2 5 ... g n 5 d10 g 0 4 g 1 4 g 2 4 ... g n 4 d9 g 0 3 g 1 3 g 2 3 ... g n 3 d8 g 0 2 g 1 2 g 2 2 ... g n 2 d7 b 0 5 b 1 5 b 2 5 ... b n 5 d6 b 0 4 b 1 4 b 2 4 ... b n 4 d5 b 0 3 b 1 3 b 2 3 ... b n 3 d4 b 0 2 b 1 2 b 2 2 ... b n 2 d3 ... d2 ... d1 ... d0 ... free datasheet http:///
page 302 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.4.5 16-bit parallel, rgb=5:6:5 when reg[0056h] bits 2-0 = 110b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 110b, the lcd2 data format is specified as this format. table 13-5: 16-bit parallel, rgb=5:6:5 data format selection cycle count 1 2 3 ... n+1 d15 r 0 5 r 1 5 r 2 5 ... r n 5 d14 r 0 4 r 1 4 r 2 4 ... r n 4 d13 r 0 3 r 1 3 r 2 3 ... r n 3 d12 r 0 2 r 1 2 r 2 2 ... r n 2 d11 r 0 1 r 1 1 r 2 1 ... r n 1 d10 g 0 5 g 1 5 g 2 5 ... g n 5 d9 g 0 4 g 1 4 g 2 4 ... g n 4 d8 g 0 3 g 1 3 g 2 3 ... g n 3 d7 g 0 2 g 1 2 g 2 2 ... g n 2 d6 g 0 1 g 1 1 g 2 1 ... g n 1 d5 g 0 0 g 1 0 g 2 0 ... g n 0 d4 b 0 5 b 1 5 b 2 5 ... b n 5 d3 b 0 4 b 1 4 b 2 4 ... b n 4 d2 b 0 3 b 1 3 b 2 3 ... b n 3 d1 b 0 2 b 1 2 b 2 2 ... b n 2 d0 b 0 1 b 1 1 b 2 1 ... b n 1 free datasheet http:///
epson research and development page 303 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.4.6 18-bit parallel, rgb=6:6:6 when reg[0056h] bits 2-0 = 111b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 111b, the lcd2 data format is specified as this format. table 13-6: 18-bit parallel, rgb=6:6:6 data format selection cycle count 1 2 3 ... n+1 d17 r 0 5 r 1 5 r 2 5 ... r n 5 d16 r 0 4 r 1 4 r 2 4 ... r n 4 d15 r 0 3 r 1 3 r 2 3 ... r n 3 d14 r 0 2 r 1 2 r 2 2 ... r n 2 d13 r 0 1 r 1 1 r 2 1 ... r n 1 d12 r 0 0 r 1 0 r 2 0 ... r n 0 d11 g 0 5 g 1 5 g 2 5 ... g n 5 d10 g 0 4 g 1 4 g 2 4 ... g n 4 d9 g 0 3 g 1 3 g 2 3 ... g n 3 d8 g 0 2 g 1 2 g 2 2 ... g n 2 d7 g 0 1 g 1 1 g 2 1 ... g n 1 d6 g 0 0 g 1 0 g 2 0 ... g n 0 d5 b 0 5 b 1 5 b 2 5 ... b n 5 d4 b 0 4 b 1 4 b 2 4 ... b n 4 d3 b 0 3 b 1 3 b 2 3 ... b n 3 d2 b 0 2 b 1 2 b 2 2 ... b n 2 d1 b 0 1 b 1 1 b 2 1 ... b n 1 d0 b 0 0 b 1 0 b 2 0 ... b n 0 free datasheet http:///
page 304 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.4.7 16-bit parallel, rgb=8:8:8 when reg[0056h] bits 2-0 = 010b, the lcd1 data format is specified as this format. when reg[005eh] bits 2-0 = 010b, the lcd2 data format is specified as this format. table 13-7: 16-bit parallel, rgb=8:8:8 data format selection cycle count 1 2 3 ... n+1 d15 r 0 7 b 0 7 g 1 7 ... r n 7 d14 r 0 6 b 0 6 g 1 6 ... r n 6 d13 r 0 5 b 0 5 g 1 5 ... r n 5 d12 r 0 4 b 0 4 g 1 4 ... r n 4 d11 r 0 3 b 0 3 g 1 3 ... r n 3 d10 r 0 2 b 0 2 g 1 2 ... r n 2 d9 r 0 1 b 0 1 g 1 1 ... r n 1 d8 r 0 0 b 0 0 g 1 0 ... r n 0 d7 g 0 7 r 1 7 b 1 7 ... g n 7 d6 g 0 6 r 1 6 b 1 6 ... g n 6 d5 g 0 5 r 1 5 b 1 5 ... g n 5 d4 g 0 4 r 1 4 b 1 4 ... g n 4 d3 g 0 3 r 1 3 b 1 3 ... g n 3 d2 g 0 2 r 1 2 b 1 2 ... g n 2 d1 g 0 1 r 1 1 b 1 1 ... g n 1 d0 g 0 0 r 1 0 b 1 0 ... g n 0 free datasheet http:///
epson research and development page 305 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.5 serial data format when the panel interface bits are set for a serial panel (reg[0032h] bits 1-0 = 00b or 10b), a serial data format must be selected. reg[005ch] bits 3-2 select the data format for lcd2. a data direction which sets either the msb or the lsb first can also be specified using reg[005ch] bit 4. note when reg[0032h] bits 1-0 = 00b, mode 1 is enabled and lcd2 is configured as a seri- al panel. when reg[0032h] bits 1-0 = 10b, mode 2 is enabled and lcd2 is configured as a serial panel. for more information on possible panel combinations, see reg[0032h] bits 1-0 in section 10.4.4, ?lcd panel interface generic setting regis- ters? on page 134. 13.5.1 8-bit serial, rgb=3:3:2 when reg[005ch] bits 1-0 = 00b, the lcd2 data format is specified as this format. 13.5.2 8-bit serial, rgb=4:4:4 when reg[005ch] bits 1-0 = 01b, the lcd2 data format is specified as this format. table 13-8: 8-bit serial, rgb=3:2:2 data format selection cycle count 1 2 3 ... n+1 d7 r 0 5 r 1 5 r 2 5 ... r n 5 d6 r 0 4 r 1 4 r 2 4 ... r n 4 d5 r 0 3 r 1 3 r 2 3 ... r n 3 d4 g 0 5 g 1 5 g 2 5 ... g n 5 d3 g 0 4 g 1 4 g 2 4 ... g n 4 d2 g 0 3 g 1 3 g 2 3 ... g n 3 d1 b 0 5 b 1 5 b 2 5 ... b n 5 d0 b 0 4 b 1 4 b 2 4 ... b n 4 table 13-9: 8-bit serial, rgb=4:4:4 data format selection cycle count 1 2 3 ... 3n+1 3n+2 3n+3 d7 r 0 5 b 0 5 g 1 5 ... r n 5 b n 5 g n+1 5 d6 r 0 4 b 0 4 g 1 4 ... r n 4 b n 4 g n+1 4 d5 r 0 3 b 0 3 g 1 3 ... r n 3 b n 3 g n+1 3 d4 r 0 2 b 0 2 g 1 2 ... r n 2 b n 2 g n+1 2 d3 g 0 5 r 1 5 b 1 5 ... g n 5 r n+1 5 b n+1 5 d2 g 0 4 r 1 4 b 1 4 ... g n 4 r n+1 4 b n+1 4 d1 g 0 3 r 1 3 b 1 3 ... g n 3 r n+1 3 b n+1 3 d0 g 0 2 r 1 2 b 1 2 ... g n 2 r n+1 2 b n+1 2 free datasheet http:///
page 306 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 13.6 yuv input / output data format 13.6.1 yuv 4:2:2 data input / output format yuv 4:2:2 output format is selected when reg[0980h] bits 3-1 = 011b and yuv 4:2:2 input format is selected when reg[0980h] bits 3-1 = 001b. table 13-10: yuv 4:2:2 data format cycle count 1 2 3 4 ... 2n+1 2n+2 d15 y 0 7 y 1 7 y 2 7 y 3 7 ... y 2n 7 y 2n+1 7 d14 y 0 6 y 1 6 y 2 6 y 3 6 ... y 2n 6 y 2n+1 6 d13 y 0 5 y 1 5 y 2 5 y 3 5 ... y 2n 5 y 2n+1 5 d12 y 0 4 y 1 4 y 2 4 y 3 4 ... y 2n 4 y 2n+1 4 d11 y 0 3 y 1 3 y 2 3 y 3 3 ... y 2n 3 y 2n+1 3 d10 y 0 2 y 1 2 y 2 2 y 3 2 ... y 2n 2 y 2n+1 2 d9 y 0 1 y 1 1 y 2 1 y 3 1 ... y 2n 1 y 2n+1 1 d8 y 0 0 y 1 0 y 2 0 y 3 0 ... y 2n 0 y 2n+1 0 d7 u 0 7 v 0 7 u 2 7 v 2 7 ... u 2n 7 v 2n+1 7 d6 u 0 6 v 0 6 u 2 6 v 2 6 ... u 2n 6 v 2n+1 6 d5 u 0 5 v 0 5 u 2 5 v 2 5 ... u 2n 5 v 2n+1 5 d4 u 0 4 v 0 4 u 2 4 v 2 4 ... u 2n 4 v 2n+1 4 d3 u 0 3 v 0 3 u 2 3 v 2 3 ... u 2n 3 v 2n+1 3 d2 u 0 2 v 0 2 u 2 2 v 2 2 ... u 2n 2 v 2n+1 2 d1 u 0 1 v 0 1 u 2 1 v 2 1 ... u 2n 1 v 2n+1 1 d0 u 0 0 v 0 0 u 2 0 v 2 0 ... u 2n 0 v 2n+1 0 free datasheet http:///
epson research and development page 307 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.6.2 yuv 4:2:0 data input / output format yuv 4:2:0 format is selected when reg[0980h] bits 3-1 = 111b and yuv 4:2:2 input format is selected when reg[0980h] bits 3-1 = 101b. this data format differs between even and odd lines. the line number count starts at 0. table 13-11: yuv 4:2:0 data format (even line) cycle count 1234...2n2n+1 d15 y 0 7 y 1 7 y 2 7 y 3 7 ... y 2n 7 y 2n+1 7 d14 y 0 6 y 1 6 y 2 6 y 3 6 ... y 2n 6 y 2n+1 6 d13 y 0 5 y 1 5 y 2 5 y 3 5 ... y 2n 5 y 2n+1 5 d12 y 0 4 y 1 4 y 2 4 y 3 4 ... y 2n 4 y 2n+1 4 d11 y 0 3 y 1 3 y 2 3 y 3 3 ... y 2n 3 y 2n+1 3 d10 y 0 2 y 1 2 y 2 2 y 3 2 ... y 2n 2 y 2n+1 2 d9 y 0 1 y 1 1 y 2 1 y 3 1 ... y 2n 1 y 2n+1 1 d8 y 0 0 y 1 0 y 2 0 y 3 0 ... y 2n 0 y 2n+1 0 d7 u 0 7 v 0 7 u 2 7 v 2 7 ... u 2n 7 v 2n+1 7 d6 u 0 6 v 0 6 u 2 6 v 2 6 ... u 2n 6 v 2n+1 6 d5 u 0 5 v 0 5 u 2 5 v 2 5 ... u 2n 5 v 2n+1 5 d4 u 0 4 v 0 4 u 2 4 v 2 4 ... u 2n 4 v 2n+1 4 d3 u 0 3 v 0 3 u 2 3 v 2 3 ... u 2n 3 v 2n+1 3 d2 u 0 2 v 0 2 u 2 2 v 2 2 ... u 2n 2 v 2n+1 2 d1 u 0 1 v 0 1 u 2 1 v 2 1 ... u 2n 1 v 2n+1 1 d0 u 0 0 v 0 0 u 2 0 v 2 0 ... u 2n 0 v 2n+1 0 free datasheet http:///
page 308 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential table 13-12: yuv 4:2:0 data format (odd line) cycle count 1 2 ... n+1 d15 y 1 7 y 3 7 ... y 2n+1 7 d14 y 1 6 y 3 6 ... y 2n+1 6 d13 y 1 5 y 3 5 ... y 2n+1 5 d12 y 1 4 y 3 4 ... y 2n+1 4 d11 y 1 3 y 3 3 ... y 2n+1 3 d10 y 1 2 y 3 2 ... y 2n+1 2 d9 y 1 1 y 3 1 ... y 2n+1 1 d8 y 1 0 y 3 0 ... y 2n+1 0 d7 y 0 7 y 2 7 ... y 2n 7 d6 y 0 6 y 2 6 ... y 2n 6 d5 y 0 5 y 2 5 ... y 2n 5 d4 y 0 4 y 2 4 ... y 2n 4 d3 y 0 3 y 2 3 ... y 2n 3 d2 y 0 2 y 2 2 ... y 2n 2 d1 y 0 1 y 2 1 ... y 2n 1 d0 y 0 0 y 2 0 ... y 2n 0 free datasheet http:///
epson research and development page 309 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 13.7 yuv/rgb conversion the yuv/rgb converter (yrc) converts yuv image data from the camera interface (yuv 4:2:2), from the jpeg decoder (yuv 4:4:4, yuv 4:2:2, yuv 4:2:0, yuv 4:1:1), or from the host (yuv 4:2:2, 4:2:0) to rgb data (rgb 5:6:5, rgb 8:8:8). the yuv data range input can be selected using the yrc input data type select bit (reg[0240h] bit 4) and the transfer mode can be selected using the yuv/rgb transfer mode bits (reg[0240h] bits 2-0). the yuv/rgb converter uses the following parameters and equations. . figure 13-8: yuv/rgb conversion equation 0 y 255 -128 u 127 -128 v 127 table 13-13: yuv/rgb conversion parameter table transfer mode reg[0240h] bit 2-0 color ey epb epr recommendation itu-r bt.709 001b e r 1.000 0.000 1.575 e g 1.000 -0.187 -0.468 e b 1.002 1.855 0.000 recommendation itu-r bt.470-6 system m 100b e r 1.000 0.001 1.400 e g 1.000 -0.333 -0.712 e b 1.000 1.780 0.002 recommendation itu-r bt.470-6 system b, g 101b e r 1.000 0.000 1.402 e g 1.000 -0.344 -0.714 e b 1.000 1.772 0.000 smpte 170m 110b e r 1.000 0.000 1.402 e g 1.000 -0.344 -0.714 e b 1.000 1.772 0.000 smpte 240m(1987) 111b e r 1.000 0.000 1.576 e g 1.000 -0.226 -0.477 e b 1.000 1.826 0.000 r g b e r e y e r e pb e r e pr e g e y e g e pb e g e pr e b e y e b e pb e b e pr y u v ? = free datasheet http:///
page 310 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 14 swivelview? most computer displays are refreshed in landscape orientation ? from left to right and top to bottom. computer images are stored in the same manner. swivelview? is designed to rotate the displayed image on an lcd by 90 , 180 , or 270 in a counter-clockwise direction . the rotation is done in hardware and is transparent to the user for all display buffer reads and writes. by processing the rotation in hardware, swivelview? offers a performance advantage over software rotation of the displayed image. the image is not actually rotated in the display buffer since there is no address translation during cpu read/write. the image is rotated during display refresh. free datasheet http:///
epson research and development page 311 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 14.1 swivelview modes 14.1.1 90 swivelview the following figure shows how the programmer sees a portrait image and how the image is being displayed. the application image is written to the S1D13717 in the following sense: a?b?c?d. the display is refreshed by the S1D13717 in the following sense: b-d- a-c. figure 14-1: relationship between the screen image and the image refreshed in 90 swivelview. display start address the display refresh circuitry starts at pixel ?b?, therefore the display start address register must be programmed with the address of pixel ?b?. display start address = address of a + line address offset - (bpp 8) line address offset line address offset is set as byte counts per 1 line of virtual image. line address offset = virtual image width x bpp 8 memory address of a given pixel to calculate the address of pixel at any given position for the main window or pip+ window, use the following formula. memory address (x,y) = [(x - 1) + (y - 1) x virtual image width] x bpp 8 a b cd swivelview window a b cd image seen by programmer (= image in display buffer) swivelview window panel width panel height display image width display image height display start address address of a (panel origin) 90 swivelview image virtual image width virtual image height free datasheet http:///
page 312 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 14.1.2 180 swivelview the following figure shows how the programmer sees a landscape image and how the image is being displayed. the application image is written to the S1D13717 in the following sense: a?b?c?d. the display is refreshed by the S1D13717 in the following sense: d-c-b-a. figure 14-2: relationship between the screen image and the image refreshed in 180 swivelview. display start address the display refresh circuitry starts at pixel ?d?, therefore the display start address register must be programmed with the address of pixel ?d?. display start address = address of a + line address offset x display image height - (bpp 8) line address offset line address offset is set as byte counts per 1 line of virtual image. line address offset = virtual image width x bpp 8 memory address of a given pixel to calculate the address of pixel at any given position for the main window or pip+ window, use the following formula. memory address (x,y) = [(x - 1) + (y - 1) x virtual image height] x bpp 8 a b c d swivelview window a b c d swivelview window image seen by programmer (= image in display buffer) panel width panel height display image width display image height display start address address of a (panel origin) 180 swivelview image virtual image height virtual display image width free datasheet http:///
epson research and development page 313 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 14.1.3 270 swivelview the following figure shows how the programmer sees a portrait image and how the image is being displayed. the application image is written to the S1D13717 in the following sense: a?b?c?d. the display is refreshed by the S1D13717 in the following sense: c-a- d-b. figure 14-3: relationship between the screen image and the image refreshed in 270 swivelview. display start address the display refresh circuitry starts at pixel ?c?, therefore the display start address register must be programmed with the address of pixel ?c?. display start address = address of a + line address offset (display image width - 1) line address offset line address offset is set as byte counts per 1 line of virtual image. line address offset = virtual image width x bpp 8 memory address of a given pixel to calculate the address of pixel at any given position for the main window or pip+ window, use the following formula. memory address (x,y) = [(x - 1) + (y - 1) x virtual image width] x bpp 8 a b cd swivelview window image seen by programmer (= image in display buffer) 270 swivelview image panel width panel height display start address (panel origin) a b cd swivelview window display image width address of a virtual image height display image height virtual image width free datasheet http:///
page 314 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 15 picture-in-picture plus (pip + ) picture-in-picture plus (pip + ) enables a secondary window (or pip + window) within the main display window. the pip + window may be positioned anywhere within the main window display and is controlled using the pip + window control registers (reg[0218h]- [0228h]). the pip + window color depth (reg[0200h] bits 3-2) and swivelview orien- tation (reg[0202h] bits 5-4) are independent from the main window. the following diagrams show examples of a pip + window within a main window and the registers used to position it. figure 15-1: pip + with swivelview disabled (swivelview 0) figure 15-2: pip + with swivelview 90 enabled pip + window main window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position swivelview tm 0 (reg[0220h] bits 9-0) (reg[0224h] bits 9-0) (reg[0226h] bits 9-0) (reg[0222h] bits 9-0) pip + window main window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position swivelview tm 90 (reg[0224h] bits 9-0) (reg[0220h] bits 9-0) (reg[0222h] bits 9-0) (reg[0226h] bits 9-0) free datasheet http:///
epson research and development page 315 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 15-3: pip + with swivelview 180 enabled figure 15-4: pip + with swivelview 270 enabled pip + window main window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position swivelview tm 180 (reg[0224h] bits 9-0) (reg[0220h] bits 9-0) (reg[0226h] bits 9-0) (reg[0222h] bits 9-0) pip + window main window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position swivelview tm 270 (reg[0224h] bits 9-0) (reg[0226h] bits 9-0) (reg[0222h] bits 9-0) (reg[0220h] bits 9-0) free datasheet http:///
page 316 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 15.1 overlay display when picture-in-picture plus (pip + ) is enabled, the S1D13717 supports an overlay with the following functions: transparent, average, and, or, and inv. each rgb component of the overlay function key colors are set using reg[0204h]-[0208h] and reg[0304h]- [0326h]. the overlay settings are specified using the overlay key color registers for each rgb color and individual overlay key color enable bits (see reg[0328h]) as follows. table 15-1: overlay mode selection register overlay pip + window bit shift (reg[0328h] bit 15) overlay main window bit shift (reg[0328h] bit 13) display image transparent overlay key color reg[0204h] reg[0206h] reg[0208h] 0 * pip + window data 1(pip + window data)/2 average overlay key color reg[0310h] reg[0312h] reg[0314h] 0 0 ((pip + window data) + (key color data))/2 1 ((pip + window data) + (key color data)/2)/2 1 0 ((pip + window data)/2 + (key color data))/2 1 ((pip + window data)/2 + (key color data)/2)/2 and overlay key color reg[0316h] reg[0318h] reg[031ah] 0 0(pip + window data) and (key color data) 1(pip + window data) and (key color data)/2 1 0(pip + window data)/2 and (key color data) 1(pip + window data)/2 and (key color data)/2 or overlay key color reg[031ch] reg[031eh] reg[0320h] 0 0(pip + window data) or (key color data) 1(pip + window data) or (key color data)/2 1 0(pip + window data)/2 or (key color data) 1(pip + window data)/2 or (key color data)/2 inv overlay key color reg[0322h] reg[0324h] reg[0326h] 0 * negative image of (pip + window data) 1 negative image of (pip + window data)/2 free datasheet http:///
epson research and development page 317 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential the following table shows the resulting pip + window color when overlay is combined with the pip + window bit shift and the main window bit shift functions. figure 15-5: data flow for bit shift function 15.1.1 overlay display effects when pip + is disabled (reg[0200h] bits 9-8 = 00)b ? only the main window is displayed and the pip + window is ignored. when pip + is enabled (reg[0200h] bits 9-8 = 01b) ?the pip + window area ?overlays? the main window area. the overlay key color set- tings are ignored. when pip + with overlay is enabled (reg[0200h] bits 9-8 = 11b) ?the pip + window area ?overlays? the main window area only on areas of the main window where the color matches the overlay key color. for the main window area, only the main window is displayed. p7 p6 p5 p4 p3 p2 p1 p0 bit shift x2, /2 bit shift x2, /2 overlay p, m p, m/2 p/2, m p/2, m/2 lut m7 m6 m5 m4 m3 m2 m1 m0 lut p7 m3 o0 p6 m7 o1 p5 m4 o2 p4 m6 o3 p3 m5 o4 p2 m0 o5 p1 m1 o6 p0 m2 o7 p7 m3 o0 p6 m7 o1 p5 m4 o2 p4 m6 o3 p3 m5 o4 p2 m0 o5 p1 m1 o6 p0 m2 o7 0 p7 p6 p5 p4 p3 p2 p1 p0 m3 m7 m4 m6 m5 m0 m1 m2 0 o0 o1 o2 o3 o4 o5 o6 o7 p7 m3 o0 p6 m7 o1 p5 m4 o2 p4 m6 o3 p3 m5 o4 p2 m0 o5 p1 m1 o6 p0 m2 o7 0 0 o0 o1 o2 o3 o4 o5 o6 o7 and, or and, or and, or and, or free datasheet http:///
page 318 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ?for the pip + window area, if the main window data is same as the overlay key color, then the pip + window data is mixed with the main window data as specified for each overlay function (see figure 15-6: ?overlay display effects 1,? on page 318). if the main window data differs from the overlay key color, then the main window data is displayed. if two or more overlays are active, they have the following priority: trans- parent key color > average key color > and key color > or key color > inv key color. a lower priority overlay function is ignored and only the highest priority overlay function is displayed. figure 15-6: overlay display effects 1 main window image pip + window image (pip + with overlay enabled) pip + disabled set green as pip + only enabled key color pip effects overlay effects original image transparent overlay average overlay and overlay key color or overlay key color inv overlay key color set green as set green as key color set green as set green as free datasheet http:///
epson research and development page 319 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 15-7: overlay display effects 2 note if more than one overlay function is enabled, only the function with the highest priority takes effect. function priority is as follows (from highest to lowest) transparent key color > average key color > and key color > or key color > inv key color. in the case where transparent and inv overlay are enabled, the inv function is ignored. main window image pip + image transparent overlay inv overlay pip + only pip + with overlay (transparent) pip + with overlay (inv) pip + with overlay (transparent, inv) key color key color free datasheet http:///
page 320 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 16 2d bitblt engine 16.1 overview the purpose of the bitblt engine is to off-load the work of the cpu for moving pixel data to and from the cpu and display memory and also for moving pixel data from one location to another in display memory. there are 5 bitblts (bit block transfer) which are used to move pixel data from one location to another. ? read bitblt: move pixel data from display memory to cpu ? move bitblt : move pixel data from one location in display memory to another ? pattern fill bitblt : move a pixel pattern in display memory and duplicate several times to produce a larger image ? solid fill bitblt : move a single color to a location in memory the bitblt engine can perform several data functions in combination with some of the bitblt functions on the pixel data. ? rop : perform a boolean function on the pixel data ? transparency : only write pixel data of which the color does not match the transparent color. the bitblt engine supports pixel data color depths of 8 bpp and16 bpp and cpu data transfers of 16-bits or 8-bits. the destination and source bitblts can be set to be either contiguous linear blocks of memory (linear) or as a rectangular region of memory (rectangular). free datasheet http:///
epson research and development page 321 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 16.2 bitblts 16.2.1 read bitblt figure 16-1: read bitblt data flow data can be read from memory by the host cpu using the bitblt engine. the source of the data is the S1D13717 internal memory (stored as either linear or rectangular data format). the destination of the data to the host cpu can also be configured to either linear or rectangular data format. no data functions like rop, transparency or color expansion are supported for read bitblts. if these features are enabled, they are ignored. the read phase can also be set for the either the first data read at the start of the bitblt for linear or at the start of each line for rectangular. the read phase allows the user to set which byte in the data read is the first byte read from memory. 16.2.2 move bitblt figure 16-2: move bitblt data flow the move bitblt copies data from the source area in memory to the destination area. the source data can also be rop?ed with the destination data and then written back to the desti- nation. the source data can also be color expanded using the color expansion data function and then stored to the destination. transparency can also be applied to the source data. the source and the destination can be in either linear or rectangular data format. the top left hand corner of the bitblt window is always specified as the start address for the source and destination. display memory bitblt engine cpu S1D13717 destination fifo source display memory source destination destination start address source start address free datasheet http:///
page 322 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 16.2.3 pattern fill bitblt figure 16-3: pattern fill drawing the pattern fill bitblt allows an 8 x 8 pixel pattern to be duplicated multiple times to a larger area in memory as shown in the example above. the pixel pattern is stored at one location and it is read and drawn multiple times to the bitblt window. for pattern fill bitblts, the pixel pattern, which is the source data, must be linear and the destination, which is the bitblt window, must be rectangular. the source data can also be rop?ed with the destination data and then written back to the destination. the start of the pixel pattern must be aligned to a 16-bit address. the pixel pattern can be drawn to a bitblt window area of 1 x 1 pixel to a max of the bitblt width x bitblt height. display memory pixel pattern bitblt window defined by bitblt width and bitblt height the pattern is duplicated over and over again in the bitblt window the pixel pattern in this example is shown as rectangular for clarity, however it must be stored in linear format. source start address destination start address free datasheet http:///
epson research and development page 323 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 16.2.4 solid fill bitblt figure 16-4: solid fill bitblt data flow for solid fill bitblts, the foreground color is written to the destination. the foreground color can be rop?ed with the destination. the destination can also be linear or rectangular data format. for 8 bpp, the foreground color is specified by reg[8024h] bits 7-0. for 16 bpp, the foreground color is specified by reg[8024h] bits 15-0. display memory destination foreground color register destination start address free datasheet http:///
page 324 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 16.2.5 bitblt terms figure 16-5: bitblt terms memory address offset width of the display (i.e. main window width or pip+ window width) in 16-bit words. the source and destination share the memory address offsets. start address top left corner of the bitblt window specified in bytes. bitblt width width of the bitblt in pixels. bitblt height height of the bitblt in pixels. bitblt window the area of the display memory to work with. for each bitblt there is a source of data and a destination for the result data. the source is the location where the data for the data function (i.e. color expansion, rop, and trans- parency) is read from. the destination is where the data for the data function (i.e. rop) is read from and also the location where the result is written to. memory address offset bitblt width bitblt height bitblt window start address free datasheet http:///
epson research and development page 325 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 16.2.6 source and destination figure 16-6: source and destination memory address offset source start address source window destination start address destination window free datasheet http:///
page 326 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 16.3 data functions the following data functions are supported by the bitblt engine. for some bitblts these functions can be combined together for some bitblts. ? color expansion ?rop ? transparency free datasheet http:///
epson research and development page 327 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 16.3.1 rop rops allow for a boolean function to be applied to the source and destination data. the boolean function is selected using the bitblt rop code bits (reg[800ah] bits 3-0). functions such as and, or, xor, nand, nor, and others can be selected. the following example shows the results for 3 different rops with the same source and desti- nation input. figure 16-7: rop example source destination source destination source destination rop = and rop = or rop = xor rop result rop result rop result free datasheet http:///
page 328 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 16.3.2 transparency transparency allows for colors which do not match the background color to be written to the destination. this is useful when a non-square image contained in the bitblt window is to be written over another image. for example, a mouse pointer is stored in memory as a block, but when the pointer is written to the display only the color of the pointer is written and the colors around it are not. the following example shows how the source image of a mouse pointer with its color set to black and color around it set to white would appear over the destination image using transparency. the white color (which matches the background color) around the mouse pointer is not written over the destination image, yet the black mouse pointer is. figure 16-8: transparency example source destination result free datasheet http:///
epson research and development page 329 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 16.4 linear / rectangular most bitblts support linear or rectangular data formats for the source and destination. linear means that the data in memory or to be written by the host cpu is in a continuous format with no gaps between the eol (end of line) and sol (start of line). the line offset is ignored for the linear data format. the following example shows how each line of linear data is stored in display memory for a bitblt with a height of 5. note that the sol of line 2 starts right after the eol of line 1. for 8 bpp, the next sol starts in the byte after the previous lines eol. for 16 bpp, it is the word after the previous line?s eol. figure 16-9: memory linear example the following example shows how linear host cpu data is written for 16-bit writes. the sol of the next line starts in the same 16-bit data as the eol of the previous line. figure 16-10: memory linear example eol line 5 sol line 1 sol line 2 eol line 1 eol line 2 bitblt width start address bitblt window in linear format sol line 1 eol line 1 sol line 2 eol line 2 cpu data write bit 15 bit 0 eol line 5 free datasheet http:///
page 330 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential rectangular means that after each eol, the sol of the next line is the sol of the current line plus the line offset for memory accesses. for host cpu accesses, the sol of the next line is always in the data written after the data with the eol. figure 16-11: memory rectangular example the following example shows how rectangular host cpu data is written for 16-bit writes. the sol of the next line starts in the next 16-bit data after the eol of the previous line. figure 16-12: memory linear example sol line 1 eol line 1 sol line 2 eol line 2 eol line 5 start address bitblt window in rectangular format bitblt width sol line 1 eol line 1 sol line 2 eol line 2 cpu data write bit 15 bit 0 eol line 5 free datasheet http:///
epson research and development page 331 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 17 resizers resizers perform the trimming and scaling functions that can be used to ?resize? image data from the camera interface and/or the jpeg decoder. there are two resizers, one for viewing image data and one for viewing/capturing image data. image data from the camera interface (always yuv 4:2:2 format) can use either the view resizer or the capture resizer before being stored in the display memory. if image data from the camera interface is being sent to the jpeg codec for jpeg encoding, it must use the capture resizer. view and capture resizer functions are configured independently. image data from the jpeg decoder (yuv 4:4:4, yuv 4:2:2, yuv 4:2:0, yuv 4:1:1 formats) or from the host cpu can only use the view resizer before being stored in the display buffer. the resize function is a two stage process - trimming then scaling. 17.1 trimming function the trimming function is similar to cropping an image and ?trims? the unwanted portion of the image. the trimming is controlled using the resizer x/y start/end position registers (reg[0944h]-[094ah] or reg[0964h]-[096ah]). the start and end addresses programmed in these registers are limited by the size of the actual camera image or the actual size of the decoded jpeg image and must not be set to a value greater than these actual sizes. the start and end position registers are set in 1 pixel increments. free datasheet http:///
page 332 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 17-1: trimming function (0, 0) valid area invalid area original image start y start x end x end y view resizer: start x = reg[0944h] bits 10-0 start y = reg[0946h] bits 10-0 end x = reg[0948h] bits 10-0 end y = reg[094ah] bits 10-0 capture resizer: start x = reg[0964h] bits 10-0 start y = reg[0966h] bits 10-0 end x = reg[0968h] bits 10-0 end y = reg[096ah] bits 10-0 free datasheet http:///
epson research and development page 333 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 17.2 scaling function the scaling function takes place after the trimming stage and it specifies the desired compression ratio to be applied to the image. when image data is scaled by the capture resizer for jpeg encoding, the jpeg codec size registers must be set for the image size after scaling. figure 17-2: scaling example (1/2 scaling) 17.2.1 1/2 scaling for 1/2 scaling, each 2x2 pixel block is scaled to 1 pixel. for the horizontal dimension, the scaling method can be either average or reduction (see reg[094eh] or reg[096eh]). for the vertical dimension, the scaling method is always reduction. figure 17-3: 1/2 compression x y trimmed view resizer: scaling rate = reg[094ch] bits 3-0 capture resizer: scaling rate = reg[096ch] bits 3-0 result x = reg[1010h], reg[100eh] result y = reg[1014h], reg[1012h] and scaled image 2x2 data block (0, 0) (1, 1) 1/2 scaling scaled data = {(0, 0)+(0, 1)}/2 (average) = (0, 0) (reduction) scaled data free datasheet http:///
page 334 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 17.2.2 1/3 scaling for 1/3 scaling, each 3x3 pixel block is scaled to 1 pixel. for both the horizontal and vertical dimensions, the scaling method is always reduction. figure 17-4: 1/3 scaling 17.2.3 1/4 scaling for 1/4 scaling, each 4x4 pixel block is scaled to 1 pixel. for the horizontal dimension, the scaling method can be either average or reduction (see reg[094eh] or reg[096eh]). for the vertical dimension, the scaling method is always reduction. figure 17-5: 1/4 scaling 3x3 data block (0, 0) (2, 2) scaled data = (1, 1) 1/3 scaling scaled data 4x4 data block (0, 0) (3, 3) 1/4 scaling scaled data = {(0, 1)+(1, 1)+(2, 1)+(3, 1)}/4 (average) = (1, 1) (reduction) scaled data free datasheet http:///
epson research and development page 335 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 17.2.4 1/5 scaling for 1/5 scaling, each 5x5 pixel block is scaled to 1 pixel. for both the horizontal and vertical dimensions, the scaling method is always reduction. figure 17-6: 1/5 scaling 17.2.5 1/6 scaling for 1/6 scaling, each 6x6 pixel block is scaled to 1 pixel. for both the horizontal and vertical dimensions, the scaling method is always reduction. figure 17-7: 1/6 scaling 5x5 data block (0, 0) (4, 4) scaled data = (2, 2) 1/5 scaling scaled data 6x6 data block (0, 0) (5, 5) scaled data = (2, 2) 1/6 scaling scaled data free datasheet http:///
page 336 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 17.2.6 1/7 scaling for 1/7 scaling, each 7x7 pixel block is scaled to 1 pixel. for both the horizontal and vertical dimensions, the scaling method is always reduction. figure 17-8: 1/7 scaling 17.2.7 1/8 scaling for 1/8 scaling, each 8x8 pixel block is scaled to 1 pixel. for the horizontal dimension, the scaling method can be either average or reduction (see reg[094eh] or reg[096eh]). for the vertical dimension, the scaling method is always reduction. figure 17-9: 1/8 scaling 7x7 data block (0, 0) (6, 6) scaled data = (3, 3) 1/7 scaling scaled data 8x8 data block (0, 0) (7, 7) 1/8 scaling scaled data = {(0, 3)+(1, 3)+(2, 3)+(3, 3)+(4, 3)+(5, 3)+(6, 3)+(7, 3)}/8 (average) = (3, 3) (reduction) scaled data free datasheet http:///
epson research and development page 337 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 17.3 resizer restrictions if any of the resizer registers must be changed while data is being received (from the camera interface, from the jpeg decoder, or from the host cpu), the view resizer register update vsync enable bit (reg[0940h] bit 1) or the capture resizer update vsync enable bit (reg[0960h] bit 1) must be set to 1 before changing any resizer register values. the resizer x/y start/end position registers must not be set larger than the incoming image size. the dimensions specified by the view resizer x/y start/end position registers (reg[0944h] - reg[094ah]) must be divisible by the view resizer scaling rate (reg[094ch] bits 5-0). the dimensions specified by the capture resizer x/y start/end position registers (reg[0964h] - reg[096ah]) must be divisible by the capture resizer scaling rate (reg[096ch] bits 5-0). free datasheet http:///
page 338 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential refer to the following table for a summary of the resizer horizontal restrictions. table 17-1: resizer horizontal restrictions summary yuv format scaling rate start position resolution yuv format scaling rate start position resolution yuv format scaling rate start position resolution 4:4:4 1/1 1 pixel 1 pixel 4:2:2 4:2:0 1/1 2 pixel 2 pixels yuv 4:1:1 1/1 4 pixel 4 pixels 1/2 2 pixels 1/2 2 pixels 1/2 4 pixels 1/3 3 pixels 1/3 6 pixels 1/3 12 pixels 1/4 4 pixels 1/4 4 pixels 1/4 4 pixels 1/5 5 pixels 1/5 10 pixels 1/5 20 pixels 1/6 6 pixels 1/6 6 pixels 1/6 12 pixels 1/7 7 pixels 1/7 14 pixels 1/7 28 pixels 1/8 8 pixels 1/8 8 pixels 1/8 8 pixels 1/9 9 pixels 1/9 18 pixels 1/9 36 pixels 1/10 10 pixels 1/10 10 pixels 1/10 20 pixels 1/11 11 pixels 1/11 22 pixels 1/11 44 pixels 1/12 12 pixels 1/12 12 pixels 1/12 12 pixels 1/13 13 pixels 1/13 26 pixels 1/13 52 pixels 1/14 14 pixels 1/14 14 pixels 1/14 28 pixels 1/15 15 pixels 1/15 30 pixels 1/15 60 pixels 1/16 16 pixels 1/16 16 pixels 1/16 16 pixels 1/17 17 pixels 1/17 34 pixels 1/17 68 pixels 1/18 18 pixels 1/18 18 pixels 1/18 36 pixels 1/19 19 pixels 1/19 38 pixels 1/19 76 pixels 1/20 20 pixels 1/20 20 pixels 1/20 20 pixels 1/21 21 pixels 1/21 42 pixels 1/21 84 pixels 1/22 22 pixels 1/22 22 pixels 1/22 44 pixels 1/23 23 pixels 1/23 46 pixels 1/23 92 pixels 1/24 24 pixels 1/24 24 pixels 1/24 24 pixels 1/25 25 pixels 1/25 50 pixels 1/25 100 pixels 1/26 26 pixels 1/26 26 pixels 1/26 52 pixels 1/27 27 pixels 1/27 54 pixels 1/27 108 pixels 1/28 28 pixels 1/28 28 pixels 1/28 28 pixels 1/29 29 pixels 1/29 58 pixels 1/29 116 pixels 1/30 30 pixels 1/30 30 pixels 1/30 60 pixels 1/31 31 pixels 1/31 62 pixels 1/31 124 pixels 1/32 32 pixels 1/32 32 pixels 1/32 32 pixels free datasheet http:///
epson research and development page 339 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential refer to the following table for a summary of the resizer vertical restrictions. . table 17-2: resizer vertical restrictions summary yuv format scaling rate start position resolution yuv format scaling rate start position resolution 4:4:4 4:2:2 4:1:1 1/1 1 line 1 pixel 4:2:0 1/1 2 lines 2 pixels 1/2 2 pixels 1/2 2 pixels 1/3 3 pixels 1/3 6 pixels 1/4 4 pixels 1/4 4 pixels 1/5 5 pixels 1/5 10 pixels 1/6 6 pixels 1/6 6 pixels 1/7 7 pixels 1/7 14 pixels 1/8 8 pixels 1/8 8 pixels 1/9 9 pixels 1/9 18 pixels 1/10 10 pixels 1/10 10 pixels 1/11 11 pixels 1/11 22 pixels 1/12 12 pixels 1/12 12 pixels 1/13 13 pixels 1/13 26 pixels 1/14 14 pixels 1/14 14 pixels 1/15 15 pixels 1/15 30 pixels 1/16 16 pixels 1/16 16 pixels 1/17 17 pixels 1/17 34 pixels 1/18 18 pixels 1/18 18 pixels 1/19 19 pixels 1/19 38 pixels 1/20 20 pixels 1/20 20 pixels 1/21 21 pixels 1/21 42 pixels 1/22 22 pixels 1/22 22 pixels 1/23 23 pixels 1/23 46 pixels 1/24 24 pixels 1/24 24 pixels 1/25 25 pixels 1/25 50 pixels 1/26 26 pixels 1/26 26 pixels 1/27 27 pixels 1/27 54 pixels 1/28 28 pixels 1/28 28 pixels 1/29 29 pixels 1/29 58 pixels 1/30 30 pixels 1/30 30 pixels 1/31 31 pixels 1/31 62 pixels 1/32 32 pixels 1/32 32 pixels free datasheet http:///
page 340 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 18 digital video functions the following is an overview block diagram of how the digital video functions interact. figure 18-1: digital video functions resizer camera interface camera jpeg module yuv/rgb converter view resizer capture resizer host interface jpeg codec yuv format converter jpeg line buffer jpeg fifo register interface camera interface camera fifo 8-bit to 24-bit yuv yuv yuv yuv yuv yuv yuv yuv yuv yuv jpeg jpeg 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 8-bit 16-bit 16-bit 16-bit 24-bit 24-bit 16-bit 24-bit 24-bit 24-bit m m m m m m m m m m m m m m s s s s s s s s m s s s s s s s (w) (w) (w) (w) (w) (w) (w) (w) (w) block interleave data line data, etc. register configuration m interface master s interface slave xx-bit data width (w) wait control type bus free datasheet http:///
epson research and development page 341 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 18.1 display image data from the camera interface figure 18-2: display image data from the camera interface initial reset and power-on set registers lcd output enable camera clock output enable overlay enable data from host data from camera display image free datasheet http:///
page 342 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 18.2 jpeg encode and camera data to the host figure 18-3: jpeg encode data from the camera interface image from camera interface jpeg operation enable data to host / encode process interrupt extra operation read fifo fifo flag operation complete flag jpeg encode operation is completed is on the display free datasheet http:///
epson research and development page 343 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 18.3 jpeg decode and display data from the host figure 18-4: jpeg decode and display data from the host initial reset and power-on set registers lcd output enable interrupt extra operation write jpeg data to fifo fifo flag overlay display enable jpeg operation is completed jpeg operation enable data from host / decoding process complete overlay display jpeg decoded image as background image free datasheet http:///
page 344 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 18.4 jpeg 180 rotate encode diagram figure 18-5: jpeg 180 rotate encode diagram camera jpeg codec yuv/rgb rgb interface serial 2d display fifo lut1 resizer host i/f display buffer lut2 p/s gpio system clock (pll) camera clock jpeg buffer jpeg bitblt parallel embedded sram rgb/yuv resizer pixel clock serial clock capture view fifo line interface interface interface 1st 32kb host processing of the camera input display output using swivelview 180 1st 32k byte block of the (96k byte image) camera image reg[0980h] bit 8 = 1 host stores jpeg image in 3 blocks block 2nd 32kb block 3rd 32kb block blocks into a single jpeg file using embedded rst markers free datasheet http:///
epson research and development page 345 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 19 jpeg encode/decode operation the S1D13717 jpeg codec is based on the jpeg baseline standard and the arithmetic accuracy satisfies the requirement of the compatibility test of jpeg part-2 (iso/iec10918- 2). the maximum image size is 1600 x 1200 and the image to be compressed/decompressed must be yuv format with a minimum resolution as shown in table 19-1: ?minimum resolution restrictions?. the following image restrictions must be observed for jpeg encode/decode, yuv data input from the host (only yuv 4:2:2, 4:2:0), and yuv data to the host (only yuv 4:2:2, 4:2:0). the image must be in yuv format and the minimum image resolution must be set based on the yuv format as follows. the quantization table accommodates two compression tables and four decompression tables. the huffman table accommodates two tables for each ac and dc. it is possible to insert markers (up to a 36 byte maximum size) during the encoding process. markers which can be processed and automatically translated during the decoding process are soi, sof0, sos, dqt, dht, dri, rstm and eoi. the decoding process supports yuv 4:4:4, yuv 4:2:2, yuv 4:1:1 and yuv 4:2:0, and the encoding process supports yuv 4:2:2, 4:1:1 and 4:2:0 format. rgb format is not supported. the image data processing ratio is almost less than 1/15 second at 640x480 resolution. however, the image data processing ratio is not guaranteed since it depends on the image data, the huffman table and the quantization table. table 19-1: minimum resolution restrictions yuv format minimum resolution 4:4:4 (decode only) 1x1 4:2:2 (encode/decode) 2x1 4:2:0 (encode/decode) 2x2 4:1:1 (encode/decode) 4x1 free datasheet http:///
page 346 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 19.1 jpeg features 19.1.1 jpeg fifo figure 19-1: jpeg fifo overview the jpeg fifo is mapped at the beginning of the display buffer and is programmable to a maximum size of 128k bytes using reg[09a4h]. the jpeg file size and host cpu perfor- mance should be considered when determining the jpeg fifo size. the status of the jpeg fifo can be checked using the jpeg fifo status register (reg[09a2h]). it is also possible to indicate the jpeg fifo status using interrupts via the jpeg interrupt control register (reg[0986h]). the jpeg fifo must be read by the host cpu during the jpeg encode process. there are two methods. 1. high performance - before reading the jpeg fifo, check how much data is available in the fifo using the status bits in the jpeg fifo status register (reg[09a2h]). next, read the fifo through reg[09a6h] based on the avail- able amount of data. note that the fifo must be read twice for each entry in the fifo (32-bit fifo but only 16-bit read/write port). continue to check and read the fifo until it is empty. this method offers the best performance because it is possible to transfer the block of data in the fifo without a fifo status check for each entry. if the jpeg fifo is read while no data is in the fifo, a terminate cy- cle will occur and no data will be read from the fifo. 2. low performance - before reading the jpeg fifo, confirm that the fifo is not empty using the jpeg fifo empty status bit (reg[09a2h] bit 0) and jpeg fifo threshold status bits (reg[09a2h] bits 3-2). after confirmation, read one entry from the fifo. note that the fifo must be read twice for each entry in the fifo (32-bit fifo but only 16-bit read/write port). the jpeg fifo must be written by the host cpu during the jpeg decode process. much like the methods for reading the jpeg fifo, writing to the jpeg fifo can be done entry by entry or as a block of data once it has been determined how many entries are available in the jpeg fifo.if the jpeg fifo is full and data is written to it by the host cpu, a terminate cycle will occur and no data will be read from the fifo. host bus jpeg fifo jpeg fifo buffer (8 bytes - 2 fifo entries) free datasheet http:///
epson research and development page 347 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 19.1.2 jpeg codec interrupts the jpeg codec can generate the following interrupts to avoid continuously poling the jpeg status bits. using interrupts decreases the cpu load for a jpeg process. for infor- mation on the jpeg interrupt register bits, see the register descriptions in section 10.4.14, ?jpeg module registers? on page 209. 1. jpeg codec interrupt flag (reg[0982h] bit 1) this flag is asserted when all jpeg processes have finished without errors, or during the decode process when a rst marker process error is detected. this in- terrupt flag should be enabled when rst marker error detection is enabled. however, if the rst marker is not required during the decode process, confirm that the operation has finished using the jpeg decode complete flag (reg[0982h] bit 5). for the encoding process, confirm that the operation has finished using the jpeg fifo empty flag (reg[0982h] bit 8) and the jpeg operation status bit (reg[1004h] bit 0). 2. jpeg line buffer overflow flag (reg[0982h] bit 2) if the jpeg fifo is read slower than the jpeg line buffer is written to during the encoding process, this flag is asserted when the jpeg line buffer overflows. this flag should be enabled for jpeg encoding. 3. jpeg decode marker read flag (reg[0982h] bit 4) during jpeg decoding, this flag is asserted when marker information is read from the jpeg file. marker information may include resize settings or lcd set- tings. jpeg decoding is stopping while this flag is asserted and does not restart until after this flag is cleared (reg[0986h] bit 4 = 0). 4. jpeg decode complete flag (reg[0982h] bit 5) this flag is asserted after the jpeg decode process is finished and the decom- pressed image data is stored in memory. this flag is useful as a trigger for en- abling the overlay or display of the image. 5. jpeg fifo empty flag (reg[0982h] bit 8) this flag is asserted when the jpeg fifo is empty. for the decode process, this flag is useful for timing jpeg data writes to the fifo and to identify when the jpeg decode process is finished completely. for the encode process, this flag in- dicates that the entire jpeg file has been read by the host. 6. jpeg fifo full flag (reg[0982h] bit 9) this flag is asserted when the jpeg fifo is full. for the encode process, this flag is used as a trigger for increasing the priority of host reads to the fifo. for the decode process, this flag indicates if it is possible to write data to the fifo. 7. jpeg fifo threshold trigger flag (reg[0982h] bit 10) this flag is asserted when the amount of data in the jpeg fifo meets the condi- tion programmed into the jpeg fifo trigger threshold bits (reg[09a0h] bits 5-4). this flag is useful for timing when the host will start to read jpeg com- pressed data in the fifo. free datasheet http:///
page 348 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 8. encode size limit violation flag (reg[0982h] bit 11) this flag is asserted when the compressed jpeg data size is greater than the pro- grammed size in the jpeg encode size limit registers (see reg[09b0h] - reg[09b2h]). 19.1.3 jpeg bypass modes the S1D13717 can bypass the jpeg codec in order for the host cpu to capture raw yuv data from the camera interface (yuv data capture mode). the S1D13717 can also bypass the jpeg codec in order for the host cpu to send raw yuv data to be displayed (yuv data display mode). for yuv data capture mode, yuv data is still sent to the host cpu through the jpeg fifo which is accessed through reg[09a6h]. for yuv data display mode, the jpeg fifo is bypassed and the host cpu writes yuv data directly to the jpeg line buffer using the jpeg line buffer write port (reg[09e0h]). the raw yuv data can be in either of the two yuv format as follows (yuv 4:2:2 = 2x1, yuv 4:2:0 = 2x2). yuv 4:2:2 yuv 4:2:0 nth line uyvyuyvy uyvyuyvy n+1th line uyvyuyvy yyyyyyyy free datasheet http:///
epson research and development page 349 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 19.2 example sequences 19.2.1 jpeg encoding process figure 19-2: jpeg encoding process (1 of 4) start jpeg module on jpeg codec software reset jpeg module software reset set jpeg codec registers set jpeg fifo registers set huffman table registers set quantization table registers capture resizer on capture resizer software reset capture next frame process? jpeg encode stop redo capture 2nd or later frame? reg[0980h] bit 0 = 1 reg[1002h] bit 7 = 1 reg[0980h] bit 7 = 1 reg[1000h]-[1066h] reg[09a0h]-[09ach] reg[1400h]-[17a2h] reg[1200h]-[12feh] reg[0960h] bit 0 = 1 reg[0960h] bit 7 = 1 capturing finish jpeg encode stop wait 1 frame of camera reg[098ah]=0000h jpeg status flag clear interrupt enable reg[0982h]=ffffh reg[0986h] reg[0a02h] to normal ending operation to jpeg codec process start capture next frame operation reg[098ah]=0000h free datasheet http:///
page 350 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 19-3: jpeg encoding process (2 of 4) interrupt enable jpeg codec process start reg[1002h] = 0001h wait marker insertion finish jpeg encode process start wait interrupt assertion interrupt assert reg[098ah] = 0001h jpeg encode time out reg[0a0ah] bit 15 =1 jpeg time out error process bus time out error process reg[0a00h] bit 2 =1 check and process of the other interrupt jpeg interrupt disable to wait interrupt assertion to jpeg status flag read reg[0a02h] bit 2 = 0 free datasheet http:///
epson research and development page 351 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 19-4: jpeg encoding process (3 of 4) jpeg interrupt disable jpeg status flag read reg[0986h] bit 10 = 0 fifo threshold trigger interrupt disable jpeg fifo read x 2 validdatasize > 0 to size limitation over to wait interrupt assertion reg[0982h] bit 11 = 1 reg[0982h] bit 2 = 1 reg[0982h] bit 10 = 1 check jpeg fifo valid data size to jpeg line buffer over flow validdatasize=(reg[09a8h])x4 readdatasize=readdatasize+4 validdatasize=validdatasize-4 jpeg fifo threshold trigger flag clear jpeg fifo threshold trigger interrupt enable reg[09a6h] reg[0982h] bit 10 = 1 reg[0986h] bit 10 = 1 reg[0982h] bit 1 = 1 jpeg interrupt enable reg[0a02h] bit 2 = 1 reg[1004h] bit 0 =1 check compression result to error process to calculate remaining fifo entries free datasheet http:///
page 352 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 19-5: jpeg encoding process (4 of 4) reg[09a6h] reg[0980h] bit 7 = 1 check compression result calculate remaining jpeg fifo entries remove invalid data to capture next frame process validdatasize > 0 readdatasize-encoderesult increment frame number display error message normal ending process jpeg fifo read x 2 readdatasize=readdatasize+4 validdatasize=validdatasize-4 reg[09a6h] error process size limitation over line buffer over flow redo capture? to redo capture redo capture? interrupt disable jpeg module off reg[0986h], reg[0a02h] reg[0980h] = 0000h validdatasize = encoderesult - readdatasize 0 1~3 to redo capture the jpeg module must be disabled before the view resizer enable bit (reg[0940h] bit 0) or the capture resizer enable bit (reg[0960h] bit 0) are disabled. jpeg module software reset jpeg fifo dummy read x 2 free datasheet http:///
epson research and development page 353 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 1. initialize the camera interface registers (reg[0100h]-[0124h]). 2. enable the jpeg module, set reg[0980h] bits 3-0 = 0001b. 3. initialize the jpeg codec registers. a. software reset the jpeg codec, set reg[1002h] bit 7 = 1. b. select the operation mode for encoding, set reg[1000h] bit 2 = 0. c. set the desired quantization table number (reg[1006h]) and the huffman table number (reg[1008h]). d. select the dri setting (reg[100ah]-[100ch]). e. configure the vertical pixel size (reg[100eh]-[1010h]) and the hori- zontal pixel size (reg[1012h]-[1014h]). f. set the insertion marker data in reg[1020h]-[1066h]. when reg[1000h] bit 3 = 1, the data in these registers is written to the jpeg file. unused bits must be written as ffh. g. initialize quantization table no. 0 (reg[1200h]-[127eh]) and quantization table no. 1 (reg[1280h]-[12feh]) with the following sequence. 12345678 9 10 11 1213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 free datasheet http:///
page 354 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential h. set dc huffman tables and the ac huffman tables according to iso/iec 10918 attachment k, each numerical formula is specified as follows: dc huffman table no. 0 register 0 (reg[1400h-141eh]) is set as a dc huffman table no. 0 register 1 (reg[1420h-1436h]) is set as b ac huffman table no. 0 register 0 (reg[1440h-145eh]) is set as c ac huffman table no. 0 register 1 (reg[1460h-15a2h]) is set as d dc huffman table no. 1 register 0 (reg[1600h-161eh]) is set as e dc huffman table no. 1 register 1 (reg[1620h-1636h]) is set as f ac huffman table no. 1 register 0 (reg[1640h-165eh]) is set as g ac huffman table no. 1 register 1 (reg[1660h-17a2h]) is set as h 4. set the jpeg module registers. a. enable the jpeg module and perform a jpeg software reset (reg[0980h] = 81h). b. specify the jpeg fifo size (reg[09a4h]). the fifo size is deter- mined using the following formula: jpeg fifo size = ((reg[09a4h] bits 3-0) + 1) x 4k bytes. example: for a jpeg fifo size of 12k bytes, reg[09a4h] = 2 (2 + 1) x 4kb = 12k bytes c. set the encode size limit (reg[09b0h]-[09b2h]) in bytes. to gen- erate an interrupt when the encode size limit is exceeded use the en- code size limit violation flag (reg[0982h] bit 11). d. clear the jpeg fifo (reg[09a0h] bit 2 = 1). e. set the jpeg fifo threshold trigger (reg[09a0h] bits 5-4). 5. set the capture resizer registers. the vertical and horizontal dimensions must be the same as the jpeg vertical and horizontal sizes as programmed in step 3e. a: 00h, 01h, 05h, ........, 00h, 00h 16 byte b: 00h, 01h, 02h, ........, 0ah, 0bh 12 byte c: 00h, 02h, 01h, 03h, ......01h, 7dh 16 byte d: 01h, 02h, 03h, ........, f9h, fah 162 byte e: 00h, 03h, 01h, ........, 00h, 00h 16 byte f: 00h, 01h, 02h, ........, 0ah, 0bh 12 byte g: 00h, 02h, 01h, 02h, ..., 02h, 77h 16 byte h: 00h, 01h, 02h, ........, f9h, fah 162 byte free datasheet http:///
epson research and development page 355 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 6. start the encode process. a. clear all status bits by writing reg[0982h] as ffffh b. enable the appropriate interrupts in the jpeg interrupt control regis- ter. for example, set reg[0986h] = 0e07h. c. start the jpeg operation (reg[1002h] bit 0 = 1) d. start capturing (reg[098ah] bit 0 = 1) after setting reg[1002h] bit 0 = 1, 2ms (internal system clock = 50mhz) is required to generate the markers. if reg[098ah] bit 0 is set to 1 before 2ms, capturing will start only after generating the markers (after 2 ms has passed). host cpu process 7. wait for the jpeg fifo threshold condition to be met. this can be done using the jpeg fifo threshold interrupt (see reg[0986h]) or by polling the jpeg fifo threshold status bits (reg[0982h] bits 13-12). if the interrupt method is used, the in- terrupt should be disabled after it is asserted. 8. confirm the fifo valid data size (reg[09a8h]). 9. read the jpeg fifo read/write register twice (reg[09a6h]). two reads from the 16-bit fifo read/write register are required to get the entire 32-bit fifo entry. 10. if using the interrupt method, the interrupt should be re-enabled again. 11. loop steps 7 through 9 continuously until the fifo valid data size reaches 0 (reg[09a8h] = 0) and the jpeg operation status is idle (reg[1004h] bit 0 = 0). 12. when the encode process finishes, check the actual file size with the encode size re- sult registers (reg[09b4h]-[09b6h]). 13. confirm the process is complete with the jpeg codec interrupt flag (reg[0982h] bit 1). 14. stop the jpeg codec using the jpeg start/stop control bit (reg[098ah] bit 0 = 0). free datasheet http:///
page 356 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 19.2.2 jpeg decoding process figure 19-6: jpeg decoding process (1 of 6) start soi marker retrieve eof not supported or error file to end marker retrieve eof to end retrieve marker marker appx to retrieve marker marker dqt confirm quantization table to retrieve marker marker dht confirm huffman table to retrieve marker marker sof0 confirm x size and y size y size 0 confirm line count to retrieve marker to retrieve marker to sos marker not supported or error file free datasheet http:///
epson research and development page 357 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 19-7: jpeg decoding process (2 of 6) sos to end eof not supported to end marker appx to retrieve marker format confirmed marker sof0 marker marker not supported or error file error file disable all of jpeg related interrupt jpeg module on jpeg codec software reset jpeg module software reset jpeg decode process setting to rst marker process setting reg[0986h] = 0000h reg[0980h] bit 0 = 1 reg[1002h] bit 7 = 1 reg[0980h] bit 7 = 1 reg[1000h] bit 2 = 1 free datasheet http:///
page 358 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 19-8: jpeg decoding process (3 of 6) jpeg decode process setting rst marker process setting reg[101ch] bits 1-0 (these bits should be 01 -> error detect on) reg[09a4h] bits 4-0 reg[09b8h], reg[09bah] reg[09a0h] bit 2 = 1 (resizer logic should be off during setting) jpeg fifo size set jpeg file size set jpeg fifo clear image size already known? view resize set view resize on view resize software reset pip window set jpeg interrupt clear enable jpeg interrupt to yuv image input write address set reg[0940h] bit 0 = 1 reg[0940h] bit 7 = 1 reg[0982h] = ffffh reg[0986h], reg[0a02h] bit 2 = 1 free datasheet http:///
epson research and development page 359 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 19-9: jpeg decoding process (4 of 6) enable jpeg interrupt yuv image input write address set reg[0242h], reg[0244h] reg[1002h] bit 0 = 1 jpeg codec operation start jpeg decode time out interrupt occurred jpeg decode time out error process reg[0a0ah] bit 15=1 cycle time out error process reg[0a00h] bit 2=1 confirm and proceed other interrupt to wait interrupt disable jpeg interrupt reg[0a02h] bit 2 = 0 jpeg status flag read reg[0982h] wait interrupt to jpeg interrupt process free datasheet http:///
page 360 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential figure 19-10: jpeg decoding process (5 of 6) jpeg interrupt process reg[0982h] bit 8 = 1 reg[0982h] bit 4 = 1 disable jpeg fifo empty interrupt reg[0986h] bit 8 = 0 jpeg file download reg[09a6h] (download fifo size) jpeg fifo empty flag clear jpeg fifo empty interrupt enable (remain disabled when file download is finished) confirm marker read horizontal/vertical image size (resizer logic should be off while setting) view resizer set view resizer on view resizer software reset pip + window set reg[0940h] bit 0 = 1 reg[0940h] bit 7 = 1 decode marker read flag clear reg[0986h] bit 4 = 0 to jpeg status read free datasheet http:///
epson research and development page 361 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential figure 19-11: jpeg decoding process (6 of 6) 1. enable the jpeg codec, set reg[0980h] bits 3-0 to 0001. 2. initialize the jpeg codec registers. a. software reset the jpeg codec, set reg[1002h] bit 7 to 1. b. select the operation mode for jpeg decoding, set reg[1000h] bit 2 = 1. c. set the rst marker operation setting, set reg[101ah]. 3. set the jpeg module registers. a. enable the jpeg module and perform a jpeg software reset (reg[0980h] = 81h). b. specify the jpeg fifo size (reg[09a4h]). the fifo size is deter- mined using the following formula: jpeg fifo size = ((reg[09a4h] bits 3-0) + 1) x 4k bytes. example: for a jpeg fifo size of 12k bytes, reg[09a4h] = 2 (2 + 1) x 4kb = 12k bytes c. specify the jpeg file size, set reg[09b8h]-[09bah]. d. clear the jpeg fifo (reg[09a0h] bit 2 = 1). jpeg status read reg[0982h] bit 1 =1 confirm jpeg status error reg[101eh] bits 6-3 error? error process confirm jpeg operation status reg[1004h] bit 0 jpeg operation change reg[1000h] bit 2 = 0 jpeg module off reg[0980h] bit 0 = 0 jpeg decode process end free datasheet http:///
page 362 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 4. if the image size and the yuv format are already known, set the registers for the view resizer. if they are not known, read the data after stopping the jpeg decode process using the decode marker read interrupt (reg[0986h] bit 4). 5. start decoding process. a. clear all status bits, set reg[0982h] to ffffh b. enable the appropriate interrupts in the jpeg interrupt control regis- ter. for example, set reg[0986h] = 0133h. c. start the jpeg operation (reg[1002h] bit 0 = 1). host cpu process 6. after confirming fifo valid data size (reg[09a8h]), write data to the jpeg fifo. 7. wait for fifo empty by interrupt or polling. if the decode marker read interrupt is enabled, there is an interrupt between steps 6 and 7. after reading data from the registers, disable the interrupt enable and clear the interrupt. then set the registers for the view resizer. 8. repeat steps 6 and 7 until the end of the jpeg file is detected. 9. if the jpeg decode complete interrupt is enabled, there is an interrupt when the end of file marker is written to the jpeg fifo. 10. verify that the jpeg decode operation is complete (reg[1004h] bit 0 = 0). note when accessing the jpeg fifo, an even number of accesses is needed for both encod- ing and decoding. for the encoding process, there will be up to 3 bytes of data that is not needed. discard this data and compare the data read to the final compressed file size in the encode size result register (reg[09b4h]-[09b6h]). for the decoding process, 32-bit unit data should always be written to the jpeg fifo. pad the end of the jpeg data stream with 00s to create 32-bits of data for the last jpeg fifo entry. note if the jpeg fifo is accessed after the jpeg process has completed or before the jpeg process has started, any data is considered invalid and ignored. free datasheet http:///
epson research and development page 363 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 19.2.3 yuv data capture 1. set the jpeg module registers. a. select the yuv data format, for yuv 4:2:2 set reg[0980h] bits 3-1 = 011, for yuv 4:2:0 set reg[0980h] bits 3-1 = 111b. b. enable the jpeg module and perform a jpeg software reset (reg[0980h] bit 7 = 1 and bit 0 = 1). c. specify the jpeg fifo size (reg[09a4h]). the fifo size is deter- mined using the following formula: jpeg fifo size = ((reg[09a4h] bits 3-0) + 1) x 4k bytes. example: for a jpeg fifo size of 12k bytes, reg[09a4h] = 2 (2 + 1) x 4kb = 12k bytes d. clear the jpeg fifo (reg[09a0h] bit 2 = 1). e. set the jpeg fifo threshold trigger (reg[09a0h] bits 5-4). 2. set the yuv capture size. a. configure the vertical pixel size (reg[100eh]-[1010h]) and the hori- zontal pixel size (reg[1012h]-[1014h]). these registers are used for both the jpeg codec and yuv capture. 3. set the capture resizer registers (reg[0960h - 096eh]) and reset the capture resizer. the vertical and horizontal dimensions must be the same as the jpeg vertical and hor- izontal sizes as programmed in step 2a. 4. start capturing yuv data. a. clear all status bits by writing reg[0982h] to ffffh. b. enable the appropriate interrupts in the jpeg interrupt control regis- ter. for example, set reg[0986h] = 0605h. c. to enable the jpeg fifo for yuv capture mode, set reg[1002h] bit 0 as 1. the jpeg fifo is now ready to receive yuv data. d. start capturing (reg[098ah] bit 0 = 1). at this stage, it is the host cpu?s task to access the jpeg fifo in the same way as for a jpeg encode process. yuv data capture continues until a 0 is written to reg[098ah] bit 0. free datasheet http:///
page 364 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 19.2.4 yuv data display 1. set the jpeg module registers. a. select the yuv data format, for yuv 4:2:2 set reg[0980h] bits 3-1 = 001, for yuv 4:2:0 set reg[0980h] bits 3-1 = 101b. b. enable the jpeg module and perform a jpeg software reset (reg[0980h] = 81h). 2. set the yuv data display size. a. configure the vertical pixel size (reg[100eh]-[1010h]) and the hori- zontal pixel size (reg[1012h]-[1014h]). these registers are used for both the jpeg codec and yuv capture. 3. set the capture resizer registers (reg[0960h - 096eh]) and reset the capture resizer. the vertical and horizontal dimensions must be the same as the jpeg vertical and hor- izontal sizes as programmed in step 2a. 4. set the jpeg line buffer registers (if the jpeg line buffer empty interrupt is used). a. set reg[09c6h] bit 0 =1 and set reg[0986h] bit 0 = 1. b. clear the jpeg line buffer status bits (reg[09c0h] = ffffh). 5. start yuv data input. a. clear all jpeg status bits (reg[0982h] = ffffh). b. enable the appropriate interrupts in the jpeg interrupt control regis- ter. for example, set reg[0986h] = 0001h. c. write yuv data to the jpeg line buffer write port (reg[09e0h]) when the jpeg line buffer is empty. the following table shows the maximum data size which can be sent at one time. the minimum line unit for yuv 4:2:2 is 1, for yuv 4:2:0 it is 2. after writing the yuv data to the jpeg line buffer, clear the jpeg line buffer empty flag (reg[09c0h] bit 0 = 1). d. continue writing yuv data until all the data is sent to the jpeg line buffer. line size the maximum data size > 256 line data size x 16 256 line data size x 32 128 line data size x 64 64 line data size x 128 32 line data size x 256 free datasheet http:///
epson research and development page 365 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 19.2.5 exit sequence the exit sequence is the same for all cases: jpeg decode, jpeg encode, yuv data capture, and yuv data display. 1. check the jpeg operation status bit (reg[1004h] bit 0). 2. for jpeg decode only, check the jpeg error status bits (reg[101eh] bits 6-3). 3. disable all interrupts, set reg[0986h] to 0000h. 4. clear all status bits, set reg[0982h] to ffffh. 5. clear the jpeg operation select bit, write a 0 to reg[1000h] bit 2. 6. perform a jpeg software reset, write a 1 to reg[0980h] bit 7. 7. disable the jpeg codec, write a 0 to reg[0980h] bit 0. free datasheet http:///
page 366 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 20 camera interface the S1D13717 is designed with a 8-bit type 1 camera interface. type 1 cameras are defined as cameras that supply horizontal and vertical sync information and typically are programmed through an i 2 c interface. 20.1 type 1 camera the type 1 external camera module connected to either of the camera ports must satisfy the following conditions: ? the camera module must work synchronously with the S1D13717 camera clock output. ? the camera module must output vsync and hsync to the S1D13717 unless itu-r bt 656 mode is used. itu-r bt 656 mode uses embedded vsync/hsync signals in the yuv data stream. the S1D13717 fully satisfies the itu-r bt656-4 requirements. ? the camera data must be 8-bit yuv 4:2:2. the following yuv 4:2:2 data formats are supported: uyvy, vyuy, yuyv, and yuyv the following ranges for the camera yuv input data are supported. ? the input data rate is determined by the camera module pixel clock output and must be a maximum of 1/3 of the system clock. for example, when the system clock is 54mhz, the camera module can have a maximum pixel clock output of 18mhz. table 20-1: yuv input data ranges yuv straight yuv offset yc bcr straight ycbcr offset 0 y 255 0 y 255 16 y 235 16 y 235 0 u 255 -128 u 127 16 u 240 -113 u 112 0 v 255 -128 v 127 16 v 240 -113 v 112 free datasheet http:///
epson research and development page 367 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 20.2 strobe control signal when the camera interface is enabled, a strobe feature is available. the strobe output is controlled using reg[0120h]-[0124h]. the strobe control signal output pin is cmstrout and must be enabled using the strobe port enable bit (reg[0124h] bit 3). 20.2.1 generating a strobe pulse to generate a strobe pulse (cmstrout): 1. enable the camera interface and ensure that the cmvref and cmhref signals are present. itu-r bt656 data format must not be enabled (reg[0110h] bit 5 = 0). 2. set the jpeg operation mode bits (reg[0980h] bits 3-1 to 111b (jpeg encode/de- code is bypassed). 3. enable the jpeg module (reg[0980h] bit 0 = 1). 4. configure the strobe line delay (reg[0120h]), strobe pulse width (reg[0122h], and strobe pulse polarity (reg[0124h] bit 1). 5. enable the strobe control signal output port by setting the strobe port enable bit (reg[0124h] bit 3 = 1). 6. enable the strobe signal (cmstrout) by setting the strobe enable bit (reg[0124] bit 0 = 1). this bit must remain enabled for the entire duration of the delay value (reg[0124h] bits 7-4), otherwise the strobe will be disabled immediately when the strobe enable bit is set to 0. 7. generate a strobe signal (cmstrout) by setting the jpeg start/stop control bit to 1 (reg[098a] bit 0 = 1). before generating another strobe signal, the strobe must be disabled (reg[0124h] bit 0 = 0) and then enabled again (reg[0124h] bit 0 = 1). then generate the strobe pulse again by setting the jpeg start/stop control bit to 1 (reg[098a] bit 0 = 1). free datasheet http:///
page 368 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 20.2.2 strobe timing the strobe pulse (cmstrout) begins on the falling edge of cmhref after cmvref as specified by the strobe line delay timing bits (reg[0120h] bits 15-0). a zero delay (reg[0120h] bits 15-0 = 0h) starts the strobe pulse (cmstrout) on the first falling edge of cmhref after cmvref. note both the line delay and pulse width signals are specified by counting hrefs which leads to an inherent timing delay if the href signal stops. this inherent delay must be considered when programming the line delay (reg[0120h]) and pulse width (reg[0122h]) registers. figure 20-1: strobe signal output timing note the line delay (reg[0120h] bits 15-0) may be set greater than the period of the cmvref signal. jpeg start/stop control bit* cmstrout next frame (reg[098a] bit 0) cmvref line delay pulse width cmhref (reg[0122h] bits 15-0 + 1 line) ((reg[0120h] bits 15-0) +1) free datasheet http:///
epson research and development page 369 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 21 sd memory card interface the S1D13717 sd memory card interface is compatible with the sd memory card physical layer specification version 1.0. either a 1-bit or 4-bit interface can be selected. this implementation of the sd memory card interface does not support spi mode or hardware security functions. figure 21-1: sd memory card interface block diagram host interface card sdcmd sddat[3:0] sdclk sdcd# sdwp data interface command interface ram 224kb data response command / parameter clock generator sdgpo sd memory S1D13717 free datasheet http:///
page 370 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 21.1 interface commands the sd memory card interface supports eight different commands. send command the send command transmits the command stream to the sdcmd pin. the command stream is composed of the contents of the command register (reg[610ch] and the parameter registers (reg[6110h] - reg[6116h]). receive response the receive response command starts receiving the response stream from the sdcmd pin. there are two lengths of response streams (48 bits and 136 bits). the response data is written to the appropriate response registers for the length of the response stream (reg[6120h] - reg[613eh]). wait busy this command waits for the data pins (sddat[3:0] to be ready. receive data the receive data command receives the data stream from the sddat[3:0] pins. when data is received, it is written to memory. the data length for received data can be configured between 1-512 using the sd memory card data length registers (reg[6108h] - reg[610ah]). send data the send data command transmits the data stream from memory to the sddat[3:0] pins. the data length for sent data can be configured between 1-512 using the sd memory card data length registers (reg[6108h] - reg[610ah]). sdclk change this command initiates a new clock frequency for the sdclk pin (see reg[6104h] bit 7). send 8 clock about eight clocks are transmitted from the sdclk pin. free datasheet http:///
epson research and development page 371 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential synchronous reset this command performs a synchronous reset of the sd memory card interface. for details on this function, see the register description for reg[6104h] bit 0. 21.2 pin functions there are three pins used by the sd memory card interface. card detect the sdcd# pin detects whether a sd memory card is inserted or not. the state of this pin can be determined using the sd memory card interrupt. write protect the sdwp pin detect whether the sd memory card is write-protected or not. general output the sdgpo pin can be used to turn on/off the external pull-ups (sdcd# or sdwp) or for an led. free datasheet http:///
page 372 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 22 indirect interface the S1D13717 supports four indirect host interfaces which can be selected using cnf[4:2] (see table 5-10: ?summary of power-on/reset options,? on page 42). for an overview of the indirect host interface, see section 1.4.2, ?indirect addressing host interfaces? on page 14. for timing details, see section 7.3, ?host interface timing? on page 56. 22.1 using the indirect interface accessing the S1D13717 through the indirect interface is a two step process. see section 22.2, ?example sequences? on page 372 for example sequences of register read/writes, memory writes, and memory reads. first, a ?command write? (or register address) is written to the indirect interface memory access port register (reg[0028h] where it is stored until the next command write. for command writes, the data bus width must be 16-bit. next, a ?data read/write? is done that specifies the data to be stored or read from the register specified in the ?command write? cycle. ?data read/write? accesses to registers must be 16-bit accesses. to access the internal memory, the memory address must be written to the indirect interface memory access registers (reg[0022h]-[0024h]) by ?command write? and ?data read/write? accesses. once the memory address is stored in these registers, a ?command write? to the memory access port register reg[0028] must be done to enable memory accesses. then ?data read/write? accesses to memory can be performed and they can be either 8-bit or 16-bit accesses. once the memory ?data read/write? is complete, the address stored in reg[0022h] - 0024h] is incremented based on the auto increment bits (reg[0026h] bits 1-0). if the auto increment feature is enabled (reg[0026h] bits 1-0 = 00b or 01b), the S1D13717 can support a memory burst transfer where the host can ?data read/write? memory data continuously without issuing a ?command write? each time. for the first access the host must set the memory address registers (reg[0022h] - reg[0024h]), but after that, the host can read/write data continuously without issuing a ?command write?. note when the indirect interface is enabled, the S1D13717 uses reg[002ah], instead of the 2d bitblt data memory mapped region register (reg[10000h]). 22.2 example sequences note all example sequences are shown using the indirect 80 type 3 host interface (cnf[4:2] = 011). free datasheet http:///
epson research and development page 373 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 22.2.1 register read/write example sequence figure 22-1: register read/write? example sequence 1. write the desired register number. 2. write the data to be placed in the register. 3. write the next register number. 4. write the data to be placed in the register. 5. write the desired register number. 6. read the data from the register. 7. write the desired register number. 8. read the data from the register. 9. ........ note the data bus width for all register accesses must be 16-bit. a1 cs# weu# wel# rdu# rdl# d[7:0] d[15:8] cmd0 cmd2 cmd4 cmd6 data2 data0 data4 data6 command data write data write data read data read read cycle write cycle write cycle read cycle 12 3 4 56 78 write command write command write command write free datasheet http:///
page 374 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 22.2.2 memory write example sequence figure 22-2: memory write example sequence 1. write the register number of the indirect interface memory address register 1 (reg[0022h]). the data bus width must be 16-bit. 2. write the lower memory address (ma[15:0]) as data to reg[0022h]. the data bus width must be 16-bit. 3. write the register number of the indirect interface memory address register 2 (reg[0024h]). the data bus width must be 16-bit. 4. write the upper memory address (ma[17:16]) as data to reg[0024h]. the data bus width must be 16-bit. 5. write the register number of the indirect interface memory access port register (reg[0028h]). this write triggers burst memory access beginning with the next ac- cess. 6. write the memory data. memory accesses may be either 8-bit or 16-bit. the data loca- tion (higher or lower byte) depends on the memory address (odd or even number). in this case, the memory address is an even address and is in the lower byte. after the memory data is written the indirect interface memory address registers are incre- mented as follows: a1 cs# weu# wel# rdu# rdl# d[7:0] d[15:8] memory command 12345678910 write address1 memory data write address1 data memory command write address2 memory data write address2 data memory command write access start byte access data write memory data even address byte access data write memory data odd address word access data write memory data even address word access data write memory data even address byte access data write memory data even address free datasheet http:///
epson research and development page 375 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a low byte access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a byte access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 7. write the memory data. memory accesses may be either 8-bit or 16-bit. the data loca- tion (higher or lower byte) depends on the memory address (odd or even number). in this case, the memory address is an odd address and is in the higher byte. after the memory data is written the indirect interface memory address registers are incre- mented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a high byte access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a byte access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 8. write the memory data. after the memory data is written the indirect interface mem- ory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 9. write the memory data. after the memory data is written the indirect interface mem- ory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 10. ........ 11. if another command write is made, burst memory access mode (or auto increment) is stopped and a register access takes place. note that the indirect interface memory ad- dress registers (reg[0022h] -[0024h]) store the last incremented memory address un- til it is changed. free datasheet http:///
page 376 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential note to begin (or trigger) memory accesses, a command write to the indirect interface memory access port register (reg[0028h]) is required, however, a data write to the register is not required. a command write to reg[0028h] indicates that burst memory accesses will start from the next data write. 22.2.3 memory read example sequence figure 22-3: memory read example sequence 1. write the register number of the indirect interface memory address register 1 (reg[0022h]). the data bus width must be 16-bit. 2. write the lower memory address (ma[15:0]) as data to reg[0022h]. the data bus width must be 16-bit. 3. write the register number of the indirect interface memory address register 2 (reg[0024h]). the data bus width must be 16-bit. 4. write the upper memory address (ma[17:16]) as data to reg[0024h]. the data bus width must be 16-bit. a1 cs# weu# wel# rdu# rdl# d[7:0] d[15:8] 1 2345 678910 memory command write address1 memory data write address1 data memory command write address2 memory data write address2 data memory command write access start byte access data read memory data even address byte access data read memory data odd address word access data read memory data even address word access data read memory data even address byte access data read memory data even address free datasheet http:///
epson research and development page 377 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 5. write the register number of the indirect interface memory access port register (reg[0028h]). this write triggers burst memory access beginning with the next ac- cess. 6. read the memory data. memory accesses may be either 8-bit or 16-bit. the data loca- tion (higher or lower byte) depends on the memory address (odd or even number). in this case, the memory address is an even address and is in the lower byte. after the memory data is read the indirect interface memory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a low byte access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a byte access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 7. read the memory data. memory accesses may be either 8-bit or 16-bit. the data loca- tion (higher or lower byte) depends on the memory address (odd or even number). in this case, the memory address is an odd address and is in the higher byte. after the memory data is read the indirect interface memory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a high byte access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are not incremented because it was a byte access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 8. read the memory data. after the memory data is read the indirect interface memory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 9. read the memory data. after the memory data is read the indirect interface memory address registers are incremented as follows: ? if reg[0026h] bits 1-0 = 00b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. ? if reg[0026h] bits 1-0 = 01b, the memory address registers (reg[0022h] - [0024h]) are incremented, +2 because it was a word access. free datasheet http:///
page 378 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ? if reg[0026h] bits 1-0 = 10b, memory address registers (reg[0022h] - [0024h]) are not incremented. 10. ........ 11. if another command write is made, burst memory access mode (or auto increment) is stopped and a register access takes place. note that the indirect interface memory ad- dress registers (reg[0022h] -[0024h]) store the last incremented memory address un- til it is changed. note it is possible to perform a memory data write after a data read and vice versa without is- suing another command write. free datasheet http:///
epson research and development page 379 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 23 mechanical data figure 23-1: S1D13717 fcbga-161 pin package 8.0 0.20 die size die size 8.0 0.20 1.0 0.23 0.04 0.5 0.25 0.75 0.3 0.05 0.25 0.5 1 = 1mm 0.75 1 2 3 4 5 6 7 8 91011121314 a b c d e f g h j k l m p n top view bottom view free datasheet http:///
page 380 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential 24 references the following documents contain additional information related to the S1D13717. document numbers are listed in parenthesis after the document name. all documents can be found at the epson research and development website at www.erd.epson.com . ? S1D13717 product brief (x57a-c-001-xx) free datasheet http:///
epson research and development page 381 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential 25 sales and technical support 25.1 ordering information to order the S1D13717 mobile graphics engine, contact the epson sales representative in your area. america epson electronics america, inc. headquarters 2580 orchard parkway san jose, ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 free datasheet http:///
page 382 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential change record x57a-a-001-03 revision 3.02 - issued: september 18, 2007 ? updated epson tagline and copyright ? added product brief to references section ? updated sales and technical support addresses x57a-a-001-03 revision 3.01 ? reg[1660h] - reg[17a2h], fixed typo in table that referred to reg[17xxh] as reg[15xxh] ? reg[6100h] bits 7-4, updated divide ratio table to include 2:1 and 3:1, also added system clock frequency table x57a-a-001-03 revision 3.0 ? released as revision 3.0 (2004/06/07) ? section 5.1 S1D13717 pinout diagram (fcbga-161) - correct typo for cnf5 and cnf4 - change pins cnf5=m11 and cnf4=n12 ? section 5.2.7 miscellaneous - correct typo for cnf5 and cnf4 - change pins cnf5=m11 and cnf4=n12 x57a-a-001-02 revision 2.0 ? released as revision 2.0 (2004/04/20) ? section 5.2.2 host interface - in table 5-3 split ab[17:1] into ab[17:2] and ab1 ? section 5.2.2 host interface - delete all references to ?parallel bypass mode? as the S1D13717 does not support this mode ? section 5.4 host interface pin mapping - delete ?parallel? columns from both tables ? reg[0902h] bits 6-0 - correct the equations in bit description x57a-a-001-01 revision 1.0 ? released as revision 1.0 (2004/04/14) x57a-a-001-00 revision 0.06 ? section 6 d.c. characteristics - table 6-2 recommended operating conditions, change t opr to ?min -20, typ 25, max 70? ? reg[0056h] bit 13 - reserve this bit ? reg[0056h] bit 12 - reserve this bit ? reg[0110h] bit 10 - add this bit ? reg[0124h] - change default value to 0009h ? reg[0124h] bit 3 - make this bit strobe enable and rewrite description free datasheet http:///
epson research and development page 383 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? reg[0124h] bit 2 - make this bit strobe port data and rewrite description ? reg[0124h] bit 0 - make this bit strobe port select and rewrite description ? reg[0200h] bit 10 - correct typo in register bit table - mark as reserved ? reg[0200h] bit 6 - correct typo in register bit table - mark as reserved ? reg[0200h] bits 3-2 - reserve bits 3-2 = 11b in table ? reg[0200h] bits 1-0 - reserve bits 1-0 = 11b in table ? reg[022ch] bit 2 - reserve this bit ? reg[0240h] bits 11-10 - reserve bits 11-00 = 11b in table ? reg[0300h] bits 15-4 - correct typo in register bit table - mark as reserved ? reg[0304h] bits 15-4 - correct typo in register bit table - mark as reserved ? reg[0308h] bits 15-4 - correct typo in register bit table - mark as reserved and change register default to ffffh ? reg[030ch] bits 15-4 - correct typo in register bit table - mark as reserved ? reg[6100h] bits 7-4 - correct typo for sampling clock frequency for ~52mhz system clock, change ?~(52/1.5)mhz? to? ~(52/2)mhz? ? section 13.1.3 32 bpp mode - remove section ? section 13.2.3 32 bpp mode - remove section ? section 19.2.2 memory image jpeg encoding process - remove ? section 19.2.3 memory image jpeg encoding process from host i/f (rgb format) - remove ? section 19.2.2 jpeg decoding process - figure 19-9 jpeg decoding process (6 of 6) - change ?jpeg process is finished - reg[1002h] bit 0 = 0? to ?jpeg operation change - reg[1000h] bit 2 = 0? x57a-a-001-00 revision 0.05 ? add section 5.2.1 unused pins - bump all other 5.2.x sections up by 1 ? section 5.3 pin descriptions, re-arrange pin numbering order in tables ? section 5.3.3 camera interface - add note for cmstrout reset# state in table ? add section 7.1.2 pll clock ? reg[000eh] bits 1-0, updated v-divider bit description to clarify its effect on pll jitter and power consumption ? reg[0010h] bits 15-12, updated vco kv set bit description to clarify its effect on pll jitter and power consumption ? reg[0014h] bit 9 - unreserve this bit and name it lcd2 serial bypass mode select ? reg[0032h] bit 8 - add text ?to enable the serial port bypass...? and add note ?the lcd output port select bits...? free datasheet http:///
page 384 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ? reg[0056h] bit 13 - replace ?tristated? with ?pulled low? ? reg[0056h] bit 12 - rewrite bit description ? reg[0116h] bit 4 - correct typos in figure 10-1, change ?reg[0114h] bit 4? to ?reg[0116h] bit 4? and ?reg[0114h] bit 5? to ?reg[0116h] bit 6? ? reg[0124h] bits 7-4 - rewrite bit description ? reg[0124h] bit 3 - reserve this bit ? reg[0124h] bit 2 - unreserve this bit and name it cmstrout gpo control ? reg[0124h] bit 0 - rewrite bit description ?when this bit = 0...? ? reg[0268h] - add this reserved register ? reg[0280h] - add this reserved register ? reg[0310h] through reg[0326h] - rewrite note ?...however, if this function doesn?t apply...? ? reg[0328h] bits 4-0 - rewrite note ?...however, if this function doesn?t apply...? ? reg[0328h] bit 13 - rewrite bit description ? reg[0940h] bit 2 - correct typo in bit description change ?vertical scaling rate is controlled by reg[094eh]...? to ?vertical scaling rate is controlled by reg[094ch]...? ? reg[0980h] bits 3-1 - update description in table for 000b - remove references to rgb/yuv converter ? reg[09a0h] bit 2 - update description for sequence to clear the jpeg fifo ? reg[09a2h] bits 6-0 - update equation in description ? reg[0a00h] bit 5 - update bit description to correct typo ? reg[0a06h] bit 1 - update bit description read ?this flag is masked by reg[0a08h]...? ? reg[0a08h] bit 1 - update bit description - ?the status of this interrupt...? ? reg[1016h - 1018h] - remove note ?vertical resolutions in...? ? reg[6002h] bits 7-0 - rewrite note for each bit ? reg[6100h] bit 0 - add note ?this bit is cleared on a sd card software reset...? ? reg[6102h] bit 7 - rewrite bit description ? reg[6102h] bit 7 - change default register value to 00x1 ? reg[6106h] bit 6 - rewrite bit description ? reg[6118h - 611eh] - add note ?these registers are write only...? ? section 11.1 power-on/power-off sequence - add ?software reset? to figure 11-1: power on/power-off sequence after ?hardware reset? and remove the ?clock source select? block as per ? section 11.1.2 reset - rewrite software reset description free datasheet http:///
epson research and development page 385 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? section 11.1.3 standby mode - rewrite standby mode description ? section 20.1 type 1 camera - rewrite bulleted text ?the input data rate is determined by...? for a max 1/3 system clock x57a-a-001-00 revision 0.04 ? section 1.5.3 serial lcd interface - delete ?... except that the lcd module vsync input is not supported for serial interface panels? from end of section ? section 1.6 display features - add mirror to section ? section 1.9.1 encoder - add ?..., or to encode yuv data sent by the host cpu? to the third paragraph ? section 1.9.2 decoder - add ?..., or to send the resulting yuv decoded data back to the host cpu? to the first paragraph ? section 2.2 host cpu interface- add bullet ?m/r# and cs# inputs select between memory and register address space in 2 cs# mode? and bullet ?cpu parallel port for direct control of a parallel lcd? ? section 2.4 display modes- add bullet ?decoded by the internal jpeg decoder, resized, scaled, and downloaded to the host cpu via the jpeg fifo? ? section 2.8 picture input/output functions - add bullets ?host cpu can directly control parallel interface panels on lcd1 or lcd2? and ?encoded by the internal jpeg encoder, resized, scaled, and downloaded to the host cpu via the jpeg fifo? ? section 5.2.1 host interface - rewrite descriptions for scs#, sclk, sa0 and si ? section 5.2.2 lcd interface - rewrite descriptions ? section 8 memory allocation - re[place entire section ? section 10.1 register mapping - add ?...(for 1 cs# mode), or cs# = 1 and m/r# = 0 (for 2 cs# mode)...? to first paragraph ? reg[0028h] - change command write to index write in bit description ? reg[0054h] - add ?... for rgb displays requiring initialization through a serial inter- face? to all bit descriptions ? reg[0056h] bit 13 - rewrite bit description ?when this bit = 1...? ? reg[0056h] bit 12 - rewrite bit description ?when this bit = 1...? ? reg[0056h] bit 7 - add ?when a manual transfer has been initiated...? to bit description ? reg[005eh] bit 13 - rewrite bit description ?when this bit = 1...? ? reg[005eh] bit 12 - rewrite bit description ?when this bit = 1...? ? reg[005eh] bit 7 - add ?when a manual transfer has been initiated...? to bit description ? reg[0110h] bit 8 - rename bit and add note to bit description ? reg[0114h] bit 8 - delete note in bit description free datasheet http:///
page 386 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ? reg[0116h] bit 1 - add ?this bit is masked by the camera frame capture interrupt enable...? to bit description ? reg[0120h] - change description to read ?... the first hsync input of a camera frame...? ? reg[0200h] bits 10 and 6 - mark these bits as n/a ? reg[0202h] bit 12 - mark this bit as n/a ? reg[0212h] bit 2 - reserve this bit ? reg[0248h] bit 2 - reserve this bit ? reg[0124h] bits 7-4 - rewrite bit description ? reg[0124h] bit 0 - rewrite bit description ? reg[0200h] bit 12 - rewrite bit description ? reg[0200h] bit 7 - rewrite bit description ? reg[021eh] bits 11-0 - add note to bit description ? reg[0220h] - add note to bit description ? reg[0222h] - add note to bit description ? reg[0224h] - add note to bit description ? reg[0226h] - add note to bit description ? reg[0240h] bit 5 - rewrite bit description ? reg[0240h] bit 4 - rename bit and rewrite bit description ? reg[0260h - 0280h] - remove these reserved registers ? reg[0930h] bit 3 - add note to bit description ? reg[0930h] bits 1-0 - rewrite description for bits 1-0 = 01 in table ? reg[0944h] bit 10 - reserve this bit ? reg[094ch] bits 13-8 - rewrite bit description ? reg[094ch] bits 5-0 - rewrite bit description ? reg[096ch] bits 13-8 - rewrite bit description ? reg[096ch] bits 5-0 - rewrite bit description ? reg[0980h] bit 4 - add ?the yuv data range depends on the interface...? to bit descrip- tion ? reg[0982h] bit 11 - add note ?the encode size limit violation flag can only be cleared...? to bit description ? reg[0982h] bit 10 - add note ?the jpeg fifo threshold trigger flag can only be cleared...? to bit description free datasheet http:///
epson research and development page 387 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? reg[0982h] bit 9 - add note ?the jpeg fifo full flag can only be cleared...? to bit description ? reg[0982h] bit 8 - add note ?the jpeg fifo empty flag can only be cleared...? to bit description ? reg[0982h] bit 0 - add ?or host decode/encode...? to bit description ? reg[0984h] bit 14 - add note to bit description ? reg[0984h] bits 13-12 - add note to bit description ? reg[09a2h] - remove reserved bits 14 - 8 and mark them n/a ? reg[09a2h] bits 3-2 - changes to table ? reg[09c0h] bit 2 - add ?this bit is only valid for yuv capture/display...? to bit description ? reg[09c0h] bit 1 - add ?this bit is only valid for yuv capture/display...? to bit description ? reg[09c0h] bit 0 - rewrite bit description ? reg[09c2h] bit 2 - add ?this bit is only valid for yuv capture/display...? to bit description ? reg[09c2h] bit 1 - add ?this bit is only valid for yuv capture/display...? to bit description ? reg[09c2h] bit 0 - rewrite bit description ? reg[09c4h] bit 0 - changes to ?when this bit = 1...? in bit description ? reg[8012h] bits 4-3 - reserve these bits ? section 12.2, removed separate lines about fpcs2#, fpso, fpsclk ? section 19.1.1, added information about terminate cycles when read from an empty fifo or write to a full fifo takes place x57a-a-001-00 revision 0.03 ? reg[6100h] bits 7-4 - table 10-85 system clock frequency and sd card clock - for system clock of ~40mhz change data transfer mode to ?0011 (~10mhz)?, for system clock of ~52mhz change data transfer mode to ?0011 (~13mhz)?, for system clock of ~55mhz change data transfer mode to ?0011 (~13.75mhz)? and change sampling clock frequency to ?~(52/2)mhz? ? reg[8004h] bits 12-7 - reserve these bits ? reg[8006h] - reserve this register ? reg[800eh] bits 4-3 - reserve these bits ? figure 11-1 power-on/power-off sequence - change niovdd to siovdd ? section 11.1.1 power-on - add siovdd to step 3 ? section 11.1.6 power-on - add siovdd to step 1 free datasheet http:///
page 388 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ? section 13.8 rgb/yuv conversion - remove section x57a-a-001-00 revision 0.02 ? section 5.2 S1D13717 pinout (fdbga-160) - corrected typo for ball g3 - changed ?fpdat19? to ?fpdat9? ? section 5.2 S1D13717 pinout (fdbga-160) - corrected typo for ball d12 - changed ?db1? to ?db10? ? section 5.3 pin descriptions - multiple changes throughout section to cell and reset# state of multiple pins ? section 7.3.1 direct 80 type 1 - delete 1.8v in tables, change timings throughout ? section 7.3.2 direct 80 type 2 - delete 1.8v in tables, change timings throughout ? section 7.3.3 direct 80 type 3 - delete 1.8v in tables, change timings throughout ? section 7.3.4 direct 68 - delete 1.8v in tables, change timings throughout ? section 7.3.5 indirect 80 type 1 - delete 1.8v in tables, change timings throughout ? section 7.3.6 indirect 80 type 2 - delete 1.8v in tables, change timings throughout ? section 7.3.7 indirect 80 type 3 - delete 1.8v in tables, change timings throughout ? section 7.3.8 indirect 68 - delete 1.8v in tables, change timings throughout ? section 7.5.2 cmclkout characteristics - add section ? section 7.5.3 strobe timing - add section ? section 10.3 register restrictions - in first bullet change ?reg[030eh]? to ?reg[030ch]? ? section 10.3 register restrictions - in third bullet change ?reg[0a0eh]? to ?reg[0f00h]? ? section 10.3 register restrictions - add bullet change ?when the sd card interface is disabled...? ? reg[0034h] - remove reference to tft type 5 from note ? reg[0036h] - remove reference to tft type 5 from note ? reg[0102h] bits 4-3 - remove ?yuv data format (16-bit format)? column from table ? reg[0270h] bits 14-12 - remove second reference to 000b from first bullet ? reg[0302h] - remove register ? reg[0306h] - remove register ? reg[030ah] - remove register ? reg[030eh] - remove register ? section 11.2 power save mode functions - add sd card interface to table ? change all fcbga-160 to fcbga-161 free datasheet http:///
epson research and development page 389 vancouver design center hardware functional specification S1D13717 issue date: 2007/09/18 x57a-a-001-03 revision 3.02 - epson confidential ? reg[005eh] bit 13 - reserve this bit ? reg[005eh] bit 12 - reserve this bit ? reg[0110h] bit 13 - reserve this bit ? reg[0200h] bit 10 - reserve this bit ? reg[0200h] bit 6 - reserve this bit ? reg[021ah] bit 2 - reserve this bit ? reg[0244h] bit 2 - reserve this bit ? reg[0260h] through reg[0278h] - reserve these registers ? reg[0930h] bit 4 - reserve this bit ? reg[0940h] bit 10 - add this reserved bit ? reg[0946h] bit 10 - reserve this bit ? reg[0948h] bit 10 - reserve this bit ? reg[094ah] bit 10 - reserve this bit ? reg[0964h] bit 10 - reserve this bit ? reg[0966h] bit 10 - reserve this bit ? reg[0968h] bit 10 - reserve this bit ? reg[096ah] bit 10 - reserve this bit ? reg[09d0h] bits 2-0 - reserve 011b, 100b in table ? reg[09d2h] bits 6-0 - remove all reference to horizontal sizes other than 640 ? reg[0a00h] - move bit 7 to bit 5, make bit 7 n/a ? reg[0a02h] - move bit 7 to bit 5, make bit 7 n/a ? reg[0a04h] - move bit 7 to bit 5, make bit 7 n/a ? reg[0a40h] - move bit 7 to bit 5, make bit 7 n/a ? reg[1016h] through reg[1018h] - add to spec ? reg[6100h] bits 7-4 - reserve 0010b in table ? add section 7.5 output buffer rise/fall time v.s. capacitance (cl) x57a-a-001-00 revision 0.01 ? spec created from S1D13717 spec x52a-a-001-01 (rev 1.0) ? changed memory size from 320kb to 224kb ? updated fcbga and qfp pin diagrams and all pin# references in the pin description tables ? removed all references to ab18 free datasheet http:///
page 390 epson research and development vancouver design center S1D13717 hardware functional specification x57a-a-001-03 issue date: 2007/09/18 revision 3.02 - epson confidential ? removed all references to gpio[21:4] except in panel descriptions (need to know what to do with panel sections that use these gpios) ? removed all camera2 and 16-bit camera information ? added sd card timing ? added sd card registers at reg[6000h] ? added sd card section at section 21 ? removed section 7.6, mpeg codec interface (no camera2 interface) ? removed section 7.7, yuv digital output (no camera2 interface) ? removed camera2 references in register section (or engineering text until confirmed) ? removed camera2 references in section 20 ? section 5.6, updated lcd pin mapping and lcd bypass mode pin mapping ? section 7, removed all ?extended tft? timing ? section 10, reserved all ?extended tft? registers and removed type-h/type-d refer- ences in all other registers ? reg[0014h] bits 12-8, reserved all parallel bypass mode bits ? reg[0032h] bits 15-10, reserved the rgb panel type bits ? reg[0102h] bit 6, reserved ? reg[0110h] bits 6-4 and 3-1, updated these bits according to the 13731 bit descriptions free datasheet http:///

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